Accelerating Innovations in the New Era of HPC, 5G and Networking with Advanced 3D Packaging Technologies

Abstract

The explosion of big data along with the accelerated global socio economical transformations we are experiencing are dramatically transforming the way we live and work. These shifts are accelerating HPC, 5G, Mobile, AR/VR, IoT, Networking and AI infrastructure. Under “ More Moore ” paradigm, scaling down of new transistor and interconnect has been improved from 32nm high-K metal gate, 28nm/18nm FDSOI (Fully Depleted Silicon on Insulator), 14nm FINFET (Fin Field Effect Transistor), 7nm EUV (Extreme Ultraviolet Lithography) and down to 3nm GAA (Gate All Around). All these silicon technologies are helping to have more transistors and more functions in the system. However, developing transistors in advanced node processes is getting more challenging and costly. Consequently, further heterogeneous system integration requires solutions that go “ Beyond Moore ” paradigm. The solutions can be new system integration architecture and advanced packaging technologies [1]. For further discussion, let's discuss two memories: DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). DRAM has high density per mm2 and high latency whereas SRAM has low density per mm2 and low latency. In PC and Mobile era, low-latency SRAM was integrated into a logic as cache memory whereas high-latency DRAM was separately integrated as a discrete component that was assembled on system board or package. In new AI era where hundreds or thousands of computing cores are needed, there is a strong demand for new system architecture with low-latency, high-bandwidth and/or higher density SRAM in 3D. 3D SRAM integration is helping to have dedicated low-latency SRAM memory per computing core or cluster. Along with transistor scaling for SRAM and core logic, advanced 2.5/3D packaging technologies are essential to the success of design platforms tailored to these new demands requiring more and higher bandwidth SRAM memories next to computing logic devices with lower latency and satisfying the sharp curve of technology acceleration and adoption in new era [2]–[6]. After discussing DRAM and decoupling capacitor integration, this paper introduces the first generation of 3DIC wafer-level logic packaging technology called X-Cube and demonstrates the technology through package and functional test vehicles with stacked SRAM memories on top of a logic die.