A multi-mode blocker-tolerant GNSS receiver with CT sigma-delta ADC in 65nm CMOS

Abstract

A fully-integrated multi-mode SAW-less GNSS receiver in 65nm CMOS is presented, which supports both ordinary and high precision GNSS signals with their bandwidth covering from 4MHz to 20MHz. The receiver employs a voltage sampling RF front-end and a 2nd-order continuous-time (CT) sigma-delta ADC to provide large dynamic range, as well as simplifying the analog baseband circuits. Besides, an on-chip I/Q calibration is integrated to improve the image rejection ratio (IRR), which can be realized manually or automatically with a FPGA. Op-amp arrays are used in the analog baseband, whose power consumption is scalable for different operation modes. The receiver achieves 3dB noise figure, -31dBm in-band 1dB compression point, -15dBm out-of-band (OOB) 1dB desensitization point, 43dB IRR and a maxim 62dB SNDR ADC outputs, while consuming 40mW DC power in the narrow-band and 52.5mW in the wide-band mode respectively.