ALTICS: an advanced timing analysis system for VLSI

Abstract

Timing verification is one of the most difficult tasks In logic LSI designing. For example, in designing ASICs using automatic layout. despite the dispersion of wiring length has to be considered in clocking skew or setup/hold verification before the Layout. logic simulator cannot deal with such kinds of problems. and has a shortcoming that it can verify only those which can be activated by a given test pattern. The path analysis [I1 C21 Is another approach, however, i t has a wssibllity to detect the paths that cannot be activated and is only avallable for SimPIY smchronized circuits. Therefor, any exlsting CAD twls cannot verify the setup/hold constrafnts accurately. To overcome these problem we have developed a new timing analysis system, called ALTiCS. Thls system uses a new path analysis method. I.e., through the estlmation of logical behavlors. it can eliminate the paths that cannot be activated. Precise backward-trace for clock distribution circult relaxes the restriction on smchronlzation. Combination of two optimized Path trace realizes a setuP/hoid veriflcation within a practically acceptable mmputatlon time.