A 1V, Ka Band Prescaler with VTControl in 90nm CMOS SOI

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI:10.1109/SOI.2005.1563527

R. Ionita, M. Sanduleanu, E. Stikvoort, A. Vladimirescu

引用次数: 1

Abstract

This paper presents a static frequency divider in a 90nm PD CMOS SOI process. The divider uses a novel D-latch topology and has an operation range of 8 to 28GHz with maximum sensitivity tuning of plusmn3GHz around 22GHz. The D-latches were implemented with NMOS transistors in R-NMOS logic. A new method is proposed for tuning the sensitivity curve of the prescaler by controlling the threshold voltage of the transistors. The VT spread due to process variations is compensated too. The VT control shows an improvement of the prescaler sensitivity with forward body-biasing voltages and an increase of the frequency range with reverse body-biasing voltages. At maximum operating frequency, the power consumption of the divider is 60mW (1V supply voltage) and the active area, including buffers, is 350 times 400mum2

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基于90nm CMOS SOI的1V, Ka带VTControl预分频器

提出了一种基于90nm PD CMOS SOI工艺的静态分频器。该分频器采用新颖的d锁存器拓扑结构，工作范围为8至28GHz，最大灵敏度在22GHz左右可调谐为plusmn3GHz。d锁存器采用R-NMOS逻辑，采用NMOS晶体管实现。提出了一种通过控制晶体管的阈值电压来调整预分频器灵敏度曲线的新方法。由于工艺变化引起的VT扩散也得到了补偿。前向体偏压改善了预量器的灵敏度，反向体偏压增加了频率范围。在最大工作频率下，分压器的功耗为60mW (1V供电电压)，包括缓冲器在内的有效面积为350倍400mum2

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2005 IEEE International SOI Conference Proceedings

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