A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder

Abstract

In this paper a new self-checking multiplier which consists of an AND-matrix, a carry-save adder and a final sumbit duplicated adder is proposed. The AND-matrix and the carry-save adder are parity checked. All errors due to single stuck-at faults in the combinational part and all even or odd (soft) errors in one of the duplicated output registers are detected. The parity checked carry-save adder is implemented by use of carry-dependent sum adder cells with a single carry-out signal. Compared to a corresponding multiplier without error detection the necessary area is about 125% to 135%.