Pub Date : 2004-05-23DOI: 10.1109/ETSYM.2004.1347602
P. Girard, O. Héron, S. Pravossoudovitch, M. Renovell
In this paper, we propose a technique for an exhaustive testing of all the delay faults in the logic architecture of symmetrical FPGAs, in a Manufacturing-Oriented Test (MOT) context. Previous techniques, concerning the test of delay faults in an FPGA, have mainly focused on delay faults on interconnexions. Our technique enables the detection of delay faults in the logic architecture and can be viewed as a complementary approach to the previous ones. The method uses the reconfiguration property of the FPGA to make easier the test of delay faults. The configuration scheme consists in chaining the logic cells or the Look-Up Tables (LUTs) in a specific way. The chain connects each LUT output to one input of the next LUT. We demonstrate that the test of all the delay faults can be done with only two configurations and a reduced test sequence.
{"title":"Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs","authors":"P. Girard, O. Héron, S. Pravossoudovitch, M. Renovell","doi":"10.1109/ETSYM.2004.1347602","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347602","url":null,"abstract":"In this paper, we propose a technique for an exhaustive testing of all the delay faults in the logic architecture of symmetrical FPGAs, in a Manufacturing-Oriented Test (MOT) context. Previous techniques, concerning the test of delay faults in an FPGA, have mainly focused on delay faults on interconnexions. Our technique enables the detection of delay faults in the logic architecture and can be viewed as a complementary approach to the previous ones. The method uses the reconfiguration property of the FPGA to make easier the test of delay faults. The configuration scheme consists in chaining the logic cells or the Look-Up Tables (LUTs) in a specific way. The chain connects each LUT output to one input of the next LUT. We demonstrate that the test of all the delay faults can be done with only two configurations and a reduced test sequence.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128449136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ETSYM.2004.1347617
P. T. Gonciari, B. Al-Hashimi
Driven by the industrial need for low-cost test methodologies, the academic community and the industry alike have put forth a number of efficient test data compression (TDC) methods. In addition, the need for core-based System-on-a-Chip (SoC) test led to considerable research in test access mechanism (TAM) design. While most previous work has considered TAM design and TDC independently, this work analyzes the interrelations between the two, outlining that a minimum test time solution obtained using TAM design will not necessarily correspond to a minimum test time solution when compression is applied. This is due to the dependency of some TDC methods on test bus width and care bit density, both of which are related to test time, and hence to TAM design. Therefore, this paper illustrates the importance of considering the characteristics of the compression method when performing TAM design, and it also shows how an existing TAM design method can be enhanced toward a compression-driven solution.
{"title":"A compression-driven test access mechanism design approach","authors":"P. T. Gonciari, B. Al-Hashimi","doi":"10.1109/ETSYM.2004.1347617","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347617","url":null,"abstract":"Driven by the industrial need for low-cost test methodologies, the academic community and the industry alike have put forth a number of efficient test data compression (TDC) methods. In addition, the need for core-based System-on-a-Chip (SoC) test led to considerable research in test access mechanism (TAM) design. While most previous work has considered TAM design and TDC independently, this work analyzes the interrelations between the two, outlining that a minimum test time solution obtained using TAM design will not necessarily correspond to a minimum test time solution when compression is applied. This is due to the dependency of some TDC methods on test bus width and care bit density, both of which are related to test time, and hence to TAM design. Therefore, this paper illustrates the importance of considering the characteristics of the compression method when performing TAM design, and it also shows how an existing TAM design method can be enhanced toward a compression-driven solution.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133539264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ETSYM.2004.1347572
A. Jutman
This article describes a novel approach to fault diagnosis suitable for at-speed testing of board-level interconnect faults.This approach is based on a new parallel test pattern generator and a specifically fault detecting sequence. The test sequence has tree major advantages.At first, it detects both static and dynamic faults upon interconnects. Secondly, it allows precise on-chp at-speed fault diagnosis of interconnect faults.Third, the hardware implementation of both the test generator and the response analyzer is very efficient in terms of silicon area.
{"title":"At-speed on-chip diagnosis of board-level interconnect faults","authors":"A. Jutman","doi":"10.1109/ETSYM.2004.1347572","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347572","url":null,"abstract":"This article describes a novel approach to fault diagnosis suitable for at-speed testing of board-level interconnect faults.This approach is based on a new parallel test pattern generator and a specifically fault detecting sequence. The test sequence has tree major advantages.At first, it detects both static and dynamic faults upon interconnects. Secondly, it allows precise on-chp at-speed fault diagnosis of interconnect faults.Third, the hardware implementation of both the test generator and the response analyzer is very efficient in terms of silicon area.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116848772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ETSYM.2004.1347615
K. J. Balakrishnan, N. Touba
The entropy of a set of data is related to the amount of information that it contains and provides a theoretical bound on the amount of compression that can be achieved. While calculating entropy is well understood for fully specified data, this paper explores the use of entropy for incompletely specified test data and shows how theoretical bounds on the maximum amount of test data compression can be calculated. An algorithm for specifying don't cares to minimize entropy for fixed length symbols is presented, and it is proven to provide the lowest entropy among all ways of specifying the don't cares. The impact of different ways of partitioning the test data into symbols on entropy is studied. Different test data compression techniques are analyzed with respect to their entropy bounds. Entropy theory is used to show the limitations and advantages of certain types of test data encoding strategies.
{"title":"Relating entropy theory to test data compression","authors":"K. J. Balakrishnan, N. Touba","doi":"10.1109/ETSYM.2004.1347615","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347615","url":null,"abstract":"The entropy of a set of data is related to the amount of information that it contains and provides a theoretical bound on the amount of compression that can be achieved. While calculating entropy is well understood for fully specified data, this paper explores the use of entropy for incompletely specified test data and shows how theoretical bounds on the maximum amount of test data compression can be calculated. An algorithm for specifying don't cares to minimize entropy for fixed length symbols is presented, and it is proven to provide the lowest entropy among all ways of specifying the don't cares. The impact of different ways of partitioning the test data into symbols on entropy is studied. Different test data compression techniques are analyzed with respect to their entropy bounds. Entropy theory is used to show the limitations and advantages of certain types of test data encoding strategies.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130173755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ETSYM.2004.1347620
S. Kajihara, K. Saluja, S. Reddy
When test vectors for a full scan logic circuit include unspecified values, conventional 3-valued fault simulation may not compute the exact fault coverage for single stuck-at faults. This paper first addresses the incompleteness of logic/fault simulation based on the conventional 3-valued logic. Then we propose an enhanced method of logic/fault simulation to compute more accurate fault coverage using implicit logic values. The proposed method employs indirect implications. We also propose a new learning criterion to identify indirect implications that are not identified by earlier static learning procedure. Since some indirect implications derived from a fault-free circuit become invalid in the presence of a fault, we use a sufficient condition for an indirect implication to remain valid for the faulty circuit, and give an efficient procedure for more accurate fault simulation. Experimental results demonstrate that the proposed method reduces the number of unknown values at the circuit outputs in logic simulation, and hence it discovers several detected faults that are not declared as detected by the conventional fault simulation.
{"title":"Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values","authors":"S. Kajihara, K. Saluja, S. Reddy","doi":"10.1109/ETSYM.2004.1347620","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347620","url":null,"abstract":"When test vectors for a full scan logic circuit include unspecified values, conventional 3-valued fault simulation may not compute the exact fault coverage for single stuck-at faults. This paper first addresses the incompleteness of logic/fault simulation based on the conventional 3-valued logic. Then we propose an enhanced method of logic/fault simulation to compute more accurate fault coverage using implicit logic values. The proposed method employs indirect implications. We also propose a new learning criterion to identify indirect implications that are not identified by earlier static learning procedure. Since some indirect implications derived from a fault-free circuit become invalid in the presence of a fault, we use a sufficient condition for an indirect implication to remain valid for the faulty circuit, and give an efficient procedure for more accurate fault simulation. Experimental results demonstrate that the proposed method reduces the number of unknown values at the circuit outputs in logic simulation, and hence it discovers several detected faults that are not declared as detected by the conventional fault simulation.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114020645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ETSYM.2004.1347607
A. Dhayni, S. Mir, L. Rufer
This paper presents a Built-In-Self-Test (BIST) implementation of pseudo-random testing for Micro Electro-Mechanical Systems (MEMS). The technique is based on Impulse Response (IR) evaluation using Maximum-Length Sequences (MLS). We will demonstrate the use of this technique and move forward to find the signature that is defined as the necessary samples of the impulse response needed to carry out an efficient test. We will use Monte-Carlo simulations to find the set of all fault-free devices under test (DUT). This set defines the impulse response space and the signature space. A DUT will be judged fault-free according to its signature being inside or outside the boundaries of the signature space. Finally, the test quality will be evaluated as function of the probabilities of false acceptance and false rejection, yield and percentage of test escapes. According to these test metrics, the design parameters (length of the MLS and the precision of the analogue to digital converter ADC) will be derived.
{"title":"Mems built-in-self-test using MLS","authors":"A. Dhayni, S. Mir, L. Rufer","doi":"10.1109/ETSYM.2004.1347607","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347607","url":null,"abstract":"This paper presents a Built-In-Self-Test (BIST) implementation of pseudo-random testing for Micro Electro-Mechanical Systems (MEMS). The technique is based on Impulse Response (IR) evaluation using Maximum-Length Sequences (MLS). We will demonstrate the use of this technique and move forward to find the signature that is defined as the necessary samples of the impulse response needed to carry out an efficient test. We will use Monte-Carlo simulations to find the set of all fault-free devices under test (DUT). This set defines the impulse response space and the signature space. A DUT will be judged fault-free according to its signature being inside or outside the boundaries of the signature space. Finally, the test quality will be evaluated as function of the probabilities of false acceptance and false rejection, yield and percentage of test escapes. According to these test metrics, the design parameters (length of the MLS and the precision of the analogue to digital converter ADC) will be derived.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"352 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114025815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ETSYM.2004.1347622
V. Avendaño, V. Champac, J. Figueras
Signal integrity verification is becoming an important issue as technological process features continues to shrink and logic speed increases. Advanced technologies permit a large number of integrated devices onto chip, this characteristic enable to have high performance systems which request good levels of signal integrity. A monitoring technique for the verification of the signal integrity is presented. Two monitors are proposed in order to sense signal undershoots and overshoots at high and low logic levels respectively. The cost of the proposed verification strategy has been estimated in terms of area, extra pins and delay penalisation. Using coherent sampling, the monitors detect signal integrity violations for high speed critical signals.
{"title":"Signal integrity verification using high speed monitors","authors":"V. Avendaño, V. Champac, J. Figueras","doi":"10.1109/ETSYM.2004.1347622","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347622","url":null,"abstract":"Signal integrity verification is becoming an important issue as technological process features continues to shrink and logic speed increases. Advanced technologies permit a large number of integrated devices onto chip, this characteristic enable to have high performance systems which request good levels of signal integrity. A monitoring technique for the verification of the signal integrity is presented. Two monitors are proposed in order to sense signal undershoots and overshoots at high and low logic levels respectively. The cost of the proposed verification strategy has been estimated in terms of area, extra pins and delay penalisation. Using coherent sampling, the monitors detect signal integrity violations for high speed critical signals.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130535496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ETSYM.2004.1347657
Y. Bonhomme, T. Yoneda, H. Fujiwara, P. Girard
We propose a new scan tree architecture for test application time reduction. This technique is based on a dynamic reconfiguration mode allowing one to reduce the dependence between the test set and the final scan tree architecture. The proposed method includes two different configuration modes: the scan tree mode and the single scan mode. The proposed method does not require any additional input or output. Experimental results show up to 95% of test application time saving and test data volume reduction in comparison with a single scan chain architecture.
{"title":"An efficient scan tree design for test time reduction","authors":"Y. Bonhomme, T. Yoneda, H. Fujiwara, P. Girard","doi":"10.1109/ETSYM.2004.1347657","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347657","url":null,"abstract":"We propose a new scan tree architecture for test application time reduction. This technique is based on a dynamic reconfiguration mode allowing one to reduce the dependence between the test set and the final scan tree architecture. The proposed method includes two different configuration modes: the scan tree mode and the single scan mode. The proposed method does not require any additional input or output. Experimental results show up to 95% of test application time saving and test data volume reduction in comparison with a single scan chain architecture.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129041289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ETSYM.2004.1347597
B. Parnas, A. Pramanick, M. Elston, Toshiaki Adachi
An open architecture test system is one that allows the seamless integration of externally developed capabilities. These capabilities include both software-only solutions as well as third party hardware modules, and the software required to support them. This paper will address the topic of developing software against an open architecture test system. This will encompass both the software-only and hardware support facets of the development effort. The notion of interface-based programming as a means to achieve this goal will be presented. A set of required "pieces" will be defined for both of these development activities. The OPENSTAR? system will be used as a vehicle to motivate the discussion with a concrete example.
{"title":"Software development for an open architecture test system","authors":"B. Parnas, A. Pramanick, M. Elston, Toshiaki Adachi","doi":"10.1109/ETSYM.2004.1347597","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347597","url":null,"abstract":"An open architecture test system is one that allows the seamless integration of externally developed capabilities. These capabilities include both software-only solutions as well as third party hardware modules, and the software required to support them. This paper will address the topic of developing software against an open architecture test system. This will encompass both the software-only and hardware support facets of the development effort. The notion of interface-based programming as a means to achieve this goal will be presented. A set of required \"pieces\" will be defined for both of these development activities. The OPENSTAR? system will be used as a vehicle to motivate the discussion with a concrete example.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"5 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114016578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ETSYM.2004.1347576
O. Petre, H. Kerkho
During the past years, due to the decrease of the minimum feature size in CMOS technology, the on-chip clock frequencies have increased dramatically ranging into the GHz domain.This increase has also pushed the need for higher data-transfer rates between these high-speed ICs, in order to optimize the entire PCB system.As a result, the clock/data skew can span tens of clock cycles. In order to cope with this skew, synchronization strategies have been developed which rely on either analogue or digital multi-tap delay-lines.In order for the synchronization mechanism to function properly, all tap-delays of the delay-line should have the same values within few percentages. This paper presents a technique, based on the oscillation method, to measure tap-delays of a delay-line with an accuracy of ±10ps.A chip has also been implemented in an UMC 0.18?m CMOS technology to prove our assumption. The measurements carried out on the chip confirmed the above mentioned accuracy.
{"title":"Accurate tap-delay measurements using a di .erential oscillation technique","authors":"O. Petre, H. Kerkho","doi":"10.1109/ETSYM.2004.1347576","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347576","url":null,"abstract":"During the past years, due to the decrease of the minimum feature size in CMOS technology, the on-chip clock frequencies have increased dramatically ranging into the GHz domain.This increase has also pushed the need for higher data-transfer rates between these high-speed ICs, in order to optimize the entire PCB system.As a result, the clock/data skew can span tens of clock cycles. In order to cope with this skew, synchronization strategies have been developed which rely on either analogue or digital multi-tap delay-lines.In order for the synchronization mechanism to function properly, all tap-delays of the delay-line should have the same values within few percentages. This paper presents a technique, based on the oscillation method, to measure tap-delays of a delay-line with an accuracy of ±10ps.A chip has also been implemented in an UMC 0.18?m CMOS technology to prove our assumption. The measurements carried out on the chip confirmed the above mentioned accuracy.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116780483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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