Enabling 10µm pitch hybrid Cu-Cu IC stacking with Through Silicon Vias

Abstract

Recently imec demonstrated for the first time 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV) on 200mm wafers [1]. The top tier dies are thinned down to 25μm and bonded to the landing wafer by Cu-Cu thermo-compression [2]. Nevertheless, the path towards high volume manufacturing remains to be established. In this paper, we report about fundamental integration issues and discuss possible solutions for further process optimization. The implementation of the proposed solution substantially increased the electrical yield of Cu-Cu joining.