S. Deleonibus, C. Arena, M. Heitzmann, F. Martin, J. Lajzerowicz, F. Vinet
{"title":"Field transistors electrical behaviour in double level aluminum interconnect processes","authors":"S. Deleonibus, C. Arena, M. Heitzmann, F. Martin, J. Lajzerowicz, F. Vinet","doi":"10.1109/VMIC.1989.78060","DOIUrl":null,"url":null,"abstract":"Summary form only given. A comparison is made of the behavior of metal 2 gate NMOS field transistors using three types of double-level aluminum interconnect isolation process for submicron CMOS application. The three insulators used are permanent spin-on-glass (SOG) process, partial etchback SOG process, and totally sacrificial SOG. Six-transistor-cell CMOS 16 K SRAMs laid out with 0.8- mu m design rules have been processed using the three processes. The total etchback process gives the best results, giving values of I/sub cc/ 10 times lower than that obtained in the permanent SOG process.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VMIC.1989.78060","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Summary form only given. A comparison is made of the behavior of metal 2 gate NMOS field transistors using three types of double-level aluminum interconnect isolation process for submicron CMOS application. The three insulators used are permanent spin-on-glass (SOG) process, partial etchback SOG process, and totally sacrificial SOG. Six-transistor-cell CMOS 16 K SRAMs laid out with 0.8- mu m design rules have been processed using the three processes. The total etchback process gives the best results, giving values of I/sub cc/ 10 times lower than that obtained in the permanent SOG process.<>