On-chip digital Idn and Idp measurement by 65 nm CMOS speed monitor circuit

Abstract

An on-chip digital I_ds measurement method is proposed in this report. In the proposed method, I_ds is digitally derived from the two values measured by three ring oscillators with PN balanced, N-rich, and P-rich inverters. The first value is the frequency of the PN balanced inverter ring. The second value is the frequency difference between the N-rich and the P-rich inverter rings. The post-digital processing derives NMOS I_ds (I_dn) and PMOS I_ds (I_dp) separately. The monitor circuit was implemented by 65 nm CMOS technology. The mismatch error between the first I_ds calculated from measured frequencies, and the second I_ds directly measured for reference, was analyzed. The standard deviations of the mismatch error in I_dn and I_dp are 1.64% and 1.09%, respectively. The margin of 3sigma is within 5% which is our target tolerance for a practical application.