A thermal van der Pauw test structure

Abstract

A micromachined thermal van der Pauw test structure is reported. Similar in principle to the conventional electrical van der Pauw Greek cross test structures, it enables the in-plane thermal sheet conductivities of thin films to be determined. The analogy between the two-dimensional heat flow in thin film samples and the electrical current pattern in thin film conductors is exploited. A thermal sheet resistance of 1.87/spl times/10/sup 5/ K/W was extracted from the complete sandwich of dielectric layers of a commercial CMOS ASIC process. This is equivalent to an average in-plane thermal conductivity of the CMOS dielectric layer sandwich of /spl kappa/=1.44 Wm/sup -1/ K/sup -1/.