Geometric optimization of high performance interconnect of Rigid/Flexible/Rigid substrate for Wafer Level Packaging in Solid State Lighting applications by numerical simulations

Abstract

Wafer Level Packaging (WLP) technology for Solid State Lighting application is regarded as great potential for cost reduction. Rigid/Flexible/Rigid (RFR) substrate that is capable of transforming WLP devices from 2-dimentional into 3-dimentional devices is of enormous interest in SSL industry. In this work, numerical simulations were performed to discover the optimized geometry of interconnects in the newly developed RFR substrate to meet the harsh requirements set for SSL products. The relations of maximum temperatures in the substrate as a function of interconnect geometry and bending angle at different current levels were derived. Moreover, by using the derived relations, geometric effects on electromigration behaviours of interconnect were investigated. Suggestions were given for optimizing the geometry of interconnects and avoiding over-bending of the substrate.