C3Map and ARPSO based mapping algorithms for energy-efficient regular 3-D NoC architectures

Abstract

Mapping of Intellectual Property (IP) cores onto Network-on-Chip (NoC) architectures is a key step in NoC-based designs. Energy, bandwidth, and latency are the key parameters that need to be optimized in such designs. In this paper, we propose Centralized 3-D Mapping (C3Map) using a new octahedral traversal technique and Attractive-Repulsive Particle Swarm Optimization (ARPSO) based algorithms for mapping IP cores onto 3-D NoC architectures. These algorithms efficiently and accurately explore the multi-objective NoC design space. We formulate the IP mapping as minimization of a cost function in order to obtain Pareto optimal IP mappings. We also propose hybridization of ARPSO with known deterministic techniques. We evaluate the proposed C3Map and ARPSO based hybrid algorithms for real-life applications and E3S benchmarks. The experimental results demonstrate the efficiency and effectiveness of C3Map as we achieved significant reduction in communication energy and latency, i.e. 19.51% to 25.81% and 24.15% to 31.21% respectively w.r.t. the known techniques.