3D Monolithic Stacked 1T1R cells using Monolayer MoS2 FET and hBN RRAM Fabricated at Low (150°C) Temperature

Abstract

We demonstrate 3D monolithically integrated two-level stacked 1-transistor/1-resistor (1T1R) memory cells, using monolayer MoS2 transistors and few-layer hBN RRAMs, fabricated at temperatures below 150 °C. The stacking process is scalable to an arbitrarily large number of layers and on any substrate material without foreseeable physical limitations. The 1T1R cells can be switched with programming current < $130\ \mu\mathrm{A}$ and voltage < 1 V, close to typical CMOS logic voltages. These cells are promising for in-memory and neuromorphic computing because (1) the hBN RRAM has gradual set and reset switching due to multiple weak-filaments formed along local defects and (2) the MoS2 transistor has low off-current due to the large band gap of monolayer MoS2$(\mathrm{E}_{\mathrm{g}} > 2\ \text{eV})$. We also show that the linearity of RRAM resistance change is well-controlled by the gate voltage of the transistor.