Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614480
A. Mihaila, L. Knoll, E. Bianda, M. Bellini, S. Wirths, G. Alfieri, L. Kranz, F. Canales, Munaf T. A. Rahimo
This paper reviews the recent progress of SiC MOSFETs rated above 3.3kV. The static and dynamic performance of 3.3 and 6.5kV-rated MOSFETs will be evaluated and benchmarked against similarly rated state-of-the-art Si IGBTs. A numerical comparison between high voltage (15kV) SiC MOSFETs and IGBTs will also be provided. The paper will also attempt to comment on the future challenges facing high voltage (HV) devices in SiC technology.
本文综述了3.3kV以上SiC mosfet的研究进展。3.3和6.5 kv额定mosfet的静态和动态性能将与同等额定的最先进Si igbt进行评估和基准测试。还将提供高压(15kV) SiC mosfet和igbt之间的数值比较。本文还将尝试对SiC技术中高压(HV)器件面临的未来挑战进行评论。
{"title":"The current status and future prospects of SiC high voltage technology","authors":"A. Mihaila, L. Knoll, E. Bianda, M. Bellini, S. Wirths, G. Alfieri, L. Kranz, F. Canales, Munaf T. A. Rahimo","doi":"10.1109/IEDM.2018.8614480","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614480","url":null,"abstract":"This paper reviews the recent progress of SiC MOSFETs rated above 3.3kV. The static and dynamic performance of 3.3 and 6.5kV-rated MOSFETs will be evaluated and benchmarked against similarly rated state-of-the-art Si IGBTs. A numerical comparison between high voltage (15kV) SiC MOSFETs and IGBTs will also be provided. The paper will also attempt to comment on the future challenges facing high voltage (HV) devices in SiC technology.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117221581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614689
Wangyong Chen, Yun Li, Linlin Cai, P. Chang, G. Du, Xiaoyan Liu
The trap behaviors based 3D-Kinetic Monte Carlo (KMC) simulator is developed for statistical reliability assessment over the entire bias space. The main features include (i) physical insight into trap charging/discharging, coupling and generation/recombination behaviors for tracking trap-induced degradation of MOSFETs with multilayer gate dielectrics in the entire bias space. (ii) simulation of statistical reliability for the MOSFETs biased under arbitrary mixed stress conditions. (iii) assessment of reliability degradation in circuit operations with various Vg/Vd stress patterns and self-heating. The statistical reliability in nanosheet (NS) FETs and corresponding circuits are investigated. The impacts of the initial interface state and bulk trap density on the threshold voltage shift during the stress and relaxation phases are also analyzed.
{"title":"Entire Bias Space Statistical Reliability Simulation By 3D-KMC Method and Its Application to the Reliability Assessment of Nanosheet FETs based Circuits","authors":"Wangyong Chen, Yun Li, Linlin Cai, P. Chang, G. Du, Xiaoyan Liu","doi":"10.1109/IEDM.2018.8614689","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614689","url":null,"abstract":"The trap behaviors based 3D-Kinetic Monte Carlo (KMC) simulator is developed for statistical reliability assessment over the entire bias space. The main features include (i) physical insight into trap charging/discharging, coupling and generation/recombination behaviors for tracking trap-induced degradation of MOSFETs with multilayer gate dielectrics in the entire bias space. (ii) simulation of statistical reliability for the MOSFETs biased under arbitrary mixed stress conditions. (iii) assessment of reliability degradation in circuit operations with various Vg/Vd stress patterns and self-heating. The statistical reliability in nanosheet (NS) FETs and corresponding circuits are investigated. The impacts of the initial interface state and bulk trap density on the threshold voltage shift during the stress and relaxation phases are also analyzed.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117242954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614533
Na Wei, Bing Chen, Z. Zheng, Zhimei Cai, Rui Zhang, R. Cheng, Shiuh-Wuu Lee, Yi Zhao
In this work, novel Ge-on-Insulator (GeOI) MOSFETs with resistive-switchable gate stacks, named RFETs, are proposed and experimentally realized. The junctionless GeOI RFET and typical inversion-mode GeOI RFET are fabricated and both types of RFETs exhibit decent transistor behaviors and RRAM characteristics at the same time. Furthermore, by utilizing these two types of RFETs, a new GeOI RFET-based NAND memory is constructed and the memory functions of the arrays are experimentally demonstrated. This RFET-based NAND memory has a simple cell structure and very simplified I/O circuit in comparison with the conventional flash memory and non-volatile memory such as RRAM and MRAM. Therefore, RFETs should be promising for the applications of next-generation high density, low power memory and in-memory computing and neuromorphic computing.
{"title":"Ge-based Non-Volatile Logic-Memory Hybrid Devices for NAND Memory Application","authors":"Na Wei, Bing Chen, Z. Zheng, Zhimei Cai, Rui Zhang, R. Cheng, Shiuh-Wuu Lee, Yi Zhao","doi":"10.1109/IEDM.2018.8614533","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614533","url":null,"abstract":"In this work, novel Ge-on-Insulator (GeOI) MOSFETs with resistive-switchable gate stacks, named RFETs, are proposed and experimentally realized. The junctionless GeOI RFET and typical inversion-mode GeOI RFET are fabricated and both types of RFETs exhibit decent transistor behaviors and RRAM characteristics at the same time. Furthermore, by utilizing these two types of RFETs, a new GeOI RFET-based NAND memory is constructed and the memory functions of the arrays are experimentally demonstrated. This RFET-based NAND memory has a simple cell structure and very simplified I/O circuit in comparison with the conventional flash memory and non-volatile memory such as RRAM and MRAM. Therefore, RFETs should be promising for the applications of next-generation high density, low power memory and in-memory computing and neuromorphic computing.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125808242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614539
A. Dasgupta, P. Rastogi, D. Saha, A. Gaidhane, A. Agarwal, Y. Chauhan
We present a new multi-domain model for polarization switching in ferroelectric materials. The computationally efficient model captures the time evolution of multi-domain ferroelectrics with good accuracy along with the frequency dependent switching behavior. We have fabricated (PVDF) and measured P-E characteristics of PZT and PVDF capacitors and have validated the model with measurements. The model allows the visualization of time dependent domain switching allowing further physical insights. We have also proposed a method to extract the distribution of domain orientations experimentally.
{"title":"Modeling of Multi-domain Switching in Ferroelectric Materials: Application to Negative Capacitance FETs","authors":"A. Dasgupta, P. Rastogi, D. Saha, A. Gaidhane, A. Agarwal, Y. Chauhan","doi":"10.1109/IEDM.2018.8614539","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614539","url":null,"abstract":"We present a new multi-domain model for polarization switching in ferroelectric materials. The computationally efficient model captures the time evolution of multi-domain ferroelectrics with good accuracy along with the frequency dependent switching behavior. We have fabricated (PVDF) and measured P-E characteristics of PZT and PVDF capacitors and have validated the model with measurements. The model allows the visualization of time dependent domain switching allowing further physical insights. We have also proposed a method to extract the distribution of domain orientations experimentally.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125587908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614581
C. Lee, R. Southwick, S. Mochizuki, J. Li, Xin He Miao, M. Wang, R. Bao, I. Ok, T. Ando, P. Hashemi, D. Guo, V. Narayanan, N. Loubet, H. Jagannathan
For the first time, high electron mobility in tensile-strained SiGe channel nFinFETs outperforming Si is reported to explore the feasibility of high performance SiGe CMOS. To examine the electron mobility behaviors in SiGe channel, a series of tensile-strained SiGe nFinFETs are fabricated on various strain relaxed buffer layers by taking into account the minimum threading dislocation density and strain engineering. For SiGe $(text{Ge} > 20%)$ nFinFETs, we identify the existence of additional electron trapping site close to the conduction band edge in IL/HK, leading to the abnormal Vt shift, PBTI degradation, and low electron mobility. We also fabricated short-channel SiGe nFinFETs, which exhibit excellent cut-off behavior and electrostatics (SS ∼65mV/dec and DIBL ∼18mV at $mathrm{V}_{text{DD}}=0.7mathrm{V}$). In addition, the dynamic performance of tensile-strained SiGe CMOS against Si CMOS is evaluated by TCAD simulation based on experimental data.
{"title":"Toward High Performance SiGe Channel CMOS: Design of High Electron Mobility in SiGe nFinFETs Outperforming Si","authors":"C. Lee, R. Southwick, S. Mochizuki, J. Li, Xin He Miao, M. Wang, R. Bao, I. Ok, T. Ando, P. Hashemi, D. Guo, V. Narayanan, N. Loubet, H. Jagannathan","doi":"10.1109/IEDM.2018.8614581","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614581","url":null,"abstract":"For the first time, high electron mobility in tensile-strained SiGe channel nFinFETs outperforming Si is reported to explore the feasibility of high performance SiGe CMOS. To examine the electron mobility behaviors in SiGe channel, a series of tensile-strained SiGe nFinFETs are fabricated on various strain relaxed buffer layers by taking into account the minimum threading dislocation density and strain engineering. For SiGe $(text{Ge} > 20%)$ nFinFETs, we identify the existence of additional electron trapping site close to the conduction band edge in IL/HK, leading to the abnormal Vt shift, PBTI degradation, and low electron mobility. We also fabricated short-channel SiGe nFinFETs, which exhibit excellent cut-off behavior and electrostatics (SS ∼65mV/dec and DIBL ∼18mV at $mathrm{V}_{text{DD}}=0.7mathrm{V}$). In addition, the dynamic performance of tensile-strained SiGe CMOS against Si CMOS is evaluated by TCAD simulation based on experimental data.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115187329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614678
Chenming Hu, L. Gignac, G. Lian, Cyril Cabral, Koichi Motoyama, Hosadurga Shobha, James J. Demarest, Y. Ostrovski, C. Breslin, M. Ali, J. Benedict, Paul S. McLaughlin, Jiamin Ni, Xiao Hu Liu
Mechanisms of electromigration (EM) damage in Cu interconnects through various CMOS nodes are reviewed. Pure Cu and Cu alloy interconnects that were used down to 14 nm node can no longer satisfy the electrical current used for 10 nm node and beyond in high-performance ICs. Cu interconnects with a metal cap should be used. Cu interface diffusivity with EM activation energy of 1.6 eV was found to be the dominate EM factor in Cu lines with a Co liner and cap. The median lifetime of 7 or 10 nm node Cu with TaN/Co liner and Co cap is predicted to be over ten thousand years at 140°C with $1.5times 10^{7}mathrm{A}/text{cm}^{2}$. However, the resistivity size effect and the difficulty of scaling barrier/liner layer without defects can limit the Cu BEOL roadmap below the 7 nm node.
{"title":"Mechanisms of Electromigration Damage in Cu Interconnects","authors":"Chenming Hu, L. Gignac, G. Lian, Cyril Cabral, Koichi Motoyama, Hosadurga Shobha, James J. Demarest, Y. Ostrovski, C. Breslin, M. Ali, J. Benedict, Paul S. McLaughlin, Jiamin Ni, Xiao Hu Liu","doi":"10.1109/IEDM.2018.8614678","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614678","url":null,"abstract":"Mechanisms of electromigration (EM) damage in Cu interconnects through various CMOS nodes are reviewed. Pure Cu and Cu alloy interconnects that were used down to 14 nm node can no longer satisfy the electrical current used for 10 nm node and beyond in high-performance ICs. Cu interconnects with a metal cap should be used. Cu interface diffusivity with EM activation energy of 1.6 eV was found to be the dominate EM factor in Cu lines with a Co liner and cap. The median lifetime of 7 or 10 nm node Cu with TaN/Co liner and Co cap is predicted to be over ten thousand years at 140°C with $1.5times 10^{7}mathrm{A}/text{cm}^{2}$. However, the resistivity size effect and the difficulty of scaling barrier/liner layer without defects can limit the Cu BEOL roadmap below the 7 nm node.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116545186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614713
G. Ayele, S. Monfray, S. Ecoffey, F. Boeuf, J. Cloarec, D. Drouin, A. Souifi
This is the first demonstration of a CMOS pH-sensor using the gate protection diode of standard FDSOI transistors in the BEOL. The extremely steep switching of the drain current induced by an exploitation of the DIBL effect is used for fabrication of extremely sensitive pH-sensors. The back gate voltage at which the abrupt switching of drain current occurs depends on the potential at the gate protection diode. Integrating the pH sensing film on this diode BEOL metal, the shift depends on the pH value of the liquid which creates a proportional potential. The abrupt switching (as small as 9 mV/decade) of the drain current can give a theoretical maximum sensitivity of 6.6 decade of drain current change per unit pH. In this paper, we report an experimental sensitivity of 1.25 decade/pH which is superior to state-of-the-art CMOS pH sensors which have a maximum sensitivity of 0.9 decade/pH.
{"title":"Highly Performant Integrated pH-Sensor Using the Gate Protection Diode in the BEOL of Industrial FDSOI","authors":"G. Ayele, S. Monfray, S. Ecoffey, F. Boeuf, J. Cloarec, D. Drouin, A. Souifi","doi":"10.1109/IEDM.2018.8614713","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614713","url":null,"abstract":"This is the first demonstration of a CMOS pH-sensor using the gate protection diode of standard FDSOI transistors in the BEOL. The extremely steep switching of the drain current induced by an exploitation of the DIBL effect is used for fabrication of extremely sensitive pH-sensors. The back gate voltage at which the abrupt switching of drain current occurs depends on the potential at the gate protection diode. Integrating the pH sensing film on this diode BEOL metal, the shift depends on the pH value of the liquid which creates a proportional potential. The abrupt switching (as small as 9 mV/decade) of the drain current can give a theoretical maximum sensitivity of 6.6 decade of drain current change per unit pH. In this paper, we report an experimental sensitivity of 1.25 decade/pH which is superior to state-of-the-art CMOS pH sensors which have a maximum sensitivity of 0.9 decade/pH.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"274 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122703970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614666
H. Tian, Xuefeng Wang, Fan Wu, Yi Yang, T. Ren
Conventional von Neumann architectures feature large power consumptions due to memory wall. Partial distributed architecture using synapses and neurons can reduce the power. However, there is still data bus between image sensor and synapses/neurons, which indicates plenty room to further lower the power consumptions. Here, a novel concept of all distributed architecture using optical synapse has been proposed. An ultrasensitive artificial optical synapse based on a graphene/2D perovskite heterostructure shows very high photo-responsivity up to 730 A/W and high stability up to 74 days. Moreover, our optical synapses has unique reconfigurable light-evoked excitatory/inhibitory functions, which is the key to enable image recognition. The demonstration of an optical synapse array for direct pattern recognition shows an accuracy as high as 80%. Our results shed light on new types of neuromorphic vision applications, such as artificial eyes.
传统的冯·诺依曼架构由于内存墙的存在，功耗很大。使用突触和神经元的部分分布式架构可以降低功耗。然而，图像传感器和突触/神经元之间仍然存在数据总线，这表明有足够的空间进一步降低功耗。本文提出了一种基于光突触的全分布式架构的新概念。基于石墨烯/2D钙钛矿异质结构的超灵敏人工光学突触具有极高的光响应性，最高可达730 a /W，高稳定性可达74天。此外，我们的光学突触具有独特的可重构光诱发兴奋/抑制功能，这是实现图像识别的关键。光学突触阵列用于直接模式识别的演示显示准确率高达80%。我们的研究结果揭示了新型神经形态视觉的应用，如人工眼睛。
{"title":"High Performance 2D Perovskite/Graphene Optical Synapses as Artificial Eyes","authors":"H. Tian, Xuefeng Wang, Fan Wu, Yi Yang, T. Ren","doi":"10.1109/IEDM.2018.8614666","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614666","url":null,"abstract":"Conventional von Neumann architectures feature large power consumptions due to memory wall. Partial distributed architecture using synapses and neurons can reduce the power. However, there is still data bus between image sensor and synapses/neurons, which indicates plenty room to further lower the power consumptions. Here, a novel concept of all distributed architecture using optical synapse has been proposed. An ultrasensitive artificial optical synapse based on a graphene/2D perovskite heterostructure shows very high photo-responsivity up to 730 A/W and high stability up to 74 days. Moreover, our optical synapses has unique reconfigurable light-evoked excitatory/inhibitory functions, which is the key to enable image recognition. The demonstration of an optical synapse array for direct pattern recognition shows an accuracy as high as 80%. Our results shed light on new types of neuromorphic vision applications, such as artificial eyes.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128779812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614617
S. Van Beek, B. O’Sullivan, P. Roussel, R. Degraeve, E. Bury, J. Swerts, S. Couet, L. Souriau, S. Kundu, S. Rao, W. Kim, F. Yasin, D. Crotti, D. Linten, G. Kar
At breakdown conditions, large current flows in STT-MRAM devices. We experimentally show that this large current causes significant self-heating of 200-300°C, which impacts the reliability extrapolation to operating conditions. By measuring and analyzing breakdown at various temperatures and on different MgO thickness, we successfully incorporate self-heating into the breakdown model. We find that the 10 year lifetime is underestimated by a factor 103 at 63-percentile, to even 107 when applying percentile scaling to 1 ppm.
{"title":"Impact of self-heating on reliability predictions in STT-MRAM","authors":"S. Van Beek, B. O’Sullivan, P. Roussel, R. Degraeve, E. Bury, J. Swerts, S. Couet, L. Souriau, S. Kundu, S. Rao, W. Kim, F. Yasin, D. Crotti, D. Linten, G. Kar","doi":"10.1109/IEDM.2018.8614617","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614617","url":null,"abstract":"At breakdown conditions, large current flows in STT-MRAM devices. We experimentally show that this large current causes significant self-heating of 200-300°C, which impacts the reliability extrapolation to operating conditions. By measuring and analyzing breakdown at various temperatures and on different MgO thickness, we successfully incorporate self-heating into the breakdown model. We find that the 10 year lifetime is underestimated by a factor 103 at 63-percentile, to even 107 when applying percentile scaling to 1 ppm.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128660379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/IEDM.2018.8614572
C. Pang, Niharika Thakuria, S. Gupta, Zhihong Chen
In this work, we demonstrate a CMOS static random-access-memory (SRAM) using WSe2 as a channel material for the first time, providing comprehensive DC analyses for transition metal dichalcogenide (TMD) material-based memory applications. A tri-gate design is adopted for the n-type MOSFET, while an air-stable, oxygen plasma induced doping scheme is introduced to implement the p-type MOSFET. DC measurements of SRAM cells demonstrate a unique dynamic tunability enabled by modulating the n-FET doping level through electrostatically gating the extended source/drain regions. Furthermore, with various read/write assist techniques, SRAM operation at low $V_{DD}$ of 0.8V is achieved. Our low power demonstration and its 2D ultra-thin material nature suggest promising applications of WSe2 for flexible electronics and Internet of Things (IoT).
{"title":"First Demonstration of WSe2 Based CMOS-SRAM","authors":"C. Pang, Niharika Thakuria, S. Gupta, Zhihong Chen","doi":"10.1109/IEDM.2018.8614572","DOIUrl":"https://doi.org/10.1109/IEDM.2018.8614572","url":null,"abstract":"In this work, we demonstrate a CMOS static random-access-memory (SRAM) using WSe2 as a channel material for the first time, providing comprehensive DC analyses for transition metal dichalcogenide (TMD) material-based memory applications. A tri-gate design is adopted for the n-type MOSFET, while an air-stable, oxygen plasma induced doping scheme is introduced to implement the p-type MOSFET. DC measurements of SRAM cells demonstrate a unique dynamic tunability enabled by modulating the n-FET doping level through electrostatically gating the extended source/drain regions. Furthermore, with various read/write assist techniques, SRAM operation at low $V_{DD}$ of 0.8V is achieved. Our low power demonstration and its 2D ultra-thin material nature suggest promising applications of WSe2 for flexible electronics and Internet of Things (IoT).","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128973494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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