Brian R. Wier, Rafael Perez Martinez, Uppili S. Raghunathar, Hanbin Ying, S. Zeinolabedinzadeh, J. Cressler
{"title":"Revisiting Safe Operating Area: SiGe HBT Aging Models for Reliability-Aware Circuit Design","authors":"Brian R. Wier, Rafael Perez Martinez, Uppili S. Raghunathar, Hanbin Ying, S. Zeinolabedinzadeh, J. Cressler","doi":"10.1109/BCICTS.2018.8551087","DOIUrl":null,"url":null,"abstract":"This paper presents and validates a physics-based compact aging model for predictive simulation of hot-carrier degradation in SiGe HBTs. Separate aging functions model the effects of high-field mixed-mode and high-current Auger-hot-carrier stresses and are integrated together to provide predictive capability across a wide bias range. The variation of aging rate with device geometry and the incorporation of multiple parameter shifts due to hot carrier polysilicon degradation are explored. Additionally, aging simulation results of a driver circuit are presented to begin to demonstrate how such models may be incorporated as part of the circuit design process.","PeriodicalId":272808,"journal":{"name":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCICTS.2018.8551087","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents and validates a physics-based compact aging model for predictive simulation of hot-carrier degradation in SiGe HBTs. Separate aging functions model the effects of high-field mixed-mode and high-current Auger-hot-carrier stresses and are integrated together to provide predictive capability across a wide bias range. The variation of aging rate with device geometry and the incorporation of multiple parameter shifts due to hot carrier polysilicon degradation are explored. Additionally, aging simulation results of a driver circuit are presented to begin to demonstrate how such models may be incorporated as part of the circuit design process.
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