Considerations in the development of a gate process module for ultra-scaled GaN HEMTs

Abstract

With the overarching goal of attaining mm-wave GaN High Electron Mobility Transistors (HEMTs), vertical and lateral downscaling is of essence. Utilizing Passivation first technology (coupled with mini-FP T-gates), Schottky Gate (SG) is formed by Fluorine plasma etching, where the plasma etching allows highly defined nanoscale gate-length (Lg) features. However, it damages the crystalline structure of the top barrier layer and leads to Fluorine implantation with ramifications on the sheet carrier density(ns), mobility (μ) and threshold-voltage (VTH) shift towards enhancement mode. In this study, CF4 or NF3 etching with varying over etch times are implemented, with high temperature annealing (600–800°C) post gate recess etching to repair crystal structure damages caused by the etch process.