4-Gb/s track and hold circuit using parasitic capacitance canceller [flash ADC application]

Abstract

A 4-Gb/s track and hold (T/H) circuit with a parasitic capacitance canceller is proposed. The parasitic capacitance canceller is connected in parallel with the load capacitance of the T/H circuit and acts as a negative capacitance. The proposed T/H circuit can reduce by 26 % its chip area and by 37 % its power dissipation compared with those of a conventional one, since the cancellation circuit equivalently reduces the load capacitance of the T/H circuit. The proposed T/H circuit is applied to a 4-Gb/s 5-bit flash ADC, fabricated in a 90 nm CMOS process. Thanks to the cancellation circuit, there is not only a reduction of its power consumption but also an extension of its bandwidth. In particular, the bandwidth is extended up to 2 GHz. The measurement results show that the signal to noise and distortion ratio (SINAD) of the ADC, at 2 GHz, is improved to about 27 dB.