Jong-Hoon Kim, Soo-Min Lee, J. Sim, Byungsub Kim, Hong-June Park
{"title":"A power reduction of 37% in a differential serial link transceiver by increasing the termination resistance","authors":"Jong-Hoon Kim, Soo-Min Lee, J. Sim, Byungsub Kim, Hong-June Park","doi":"10.1109/ASSCC.2013.6691022","DOIUrl":null,"url":null,"abstract":"By increasing the termination resistance to 4ZO at both TX and RX of a differential serial link with a CML driver, the transceiver power is reduced by 37%. The TX power is reduced by 54%. The TX includes a CML driver, a pre-driver and a serializer. While the reflection and the ISI are increased due to the increase of the termination resistance, they are compensated for by a 2-tap DFE circuit at RX. The DFE tap position for reflection and the DFE coefficients for ISI and reflection are found automatically during the initial training mode. The transceiver chip fabricated in a 0.13μm process shows a BER<;1E-12 with 25, 30 and 35cm FR4 channels at 5Gbps.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2013.6691022","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
By increasing the termination resistance to 4ZO at both TX and RX of a differential serial link with a CML driver, the transceiver power is reduced by 37%. The TX power is reduced by 54%. The TX includes a CML driver, a pre-driver and a serializer. While the reflection and the ISI are increased due to the increase of the termination resistance, they are compensated for by a 2-tap DFE circuit at RX. The DFE tap position for reflection and the DFE coefficients for ISI and reflection are found automatically during the initial training mode. The transceiver chip fabricated in a 0.13μm process shows a BER<;1E-12 with 25, 30 and 35cm FR4 channels at 5Gbps.