Logic verification of very large circuits using Shark

Jeremy Casas, Hannah Honghua Yang, M. Khaira, M. Joshi, T. Tetzlaff, S. Otto, E. Seligman
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引用次数: 9

Abstract

In this paper, we will present Shark, a software based logic verification technology that allows high-performance switch-level simulation of multi-million transistor circuits on general-purpose workstations. Shark achieves high-performance simulations on very large circuits through three key technologies: 1) a circuit partitioner based on latch boundary components, design hierarchy driven clustering, and latch/activity load balancing, 2) a high-performance switch-level simulator capable of simulating very large models and run word-parallel simulations, and 3) a simulation backplane that can connect any number of simulators to form a distributed/parallel simulation environment. Shark has been tested on circuits of up to 15 M transistors. On an Intel circuit with about 5 M transistors, Shark achieved a simulation throughput of 19 Hz.
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使用Shark进行大型电路的逻辑验证
在本文中,我们将介绍Shark,这是一种基于软件的逻辑验证技术,允许在通用工作站上对数百万晶体管电路进行高性能开关级仿真。Shark通过三个关键技术实现了超大电路的高性能仿真:1)基于闩锁边界组件的电路分区器、设计层次驱动的聚类和闩锁/活动负载平衡;2)能够模拟超大模型并运行字并行仿真的高性能开关级模拟器;3)可以连接任意数量模拟器形成分布式/并行仿真环境的仿真背板。Shark已经在多达15个晶体管的电路上进行了测试。在大约5 M晶体管的英特尔电路上,Shark实现了19 Hz的模拟吞吐量。
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