A hierarchical floor-planning, placement, and routing tool for sea-of-gates designs

C. Ng, S. Ashtaputre, E. Chambers, Kieu-Huong Do, S.-T. Hui, R. Mody, D. Wong
{"title":"A hierarchical floor-planning, placement, and routing tool for sea-of-gates designs","authors":"C. Ng, S. Ashtaputre, E. Chambers, Kieu-Huong Do, S.-T. Hui, R. Mody, D. Wong","doi":"10.1109/CICC.1989.56680","DOIUrl":null,"url":null,"abstract":"The authors present an automatic layout system for designing large sea-of-gates gate arrays. This tool combines a floorplanning tool with an automatic placement and routing tool. It is designed to handle 250 K-gate arrays with special functional blocks such as RAM and ROM. It provides features for current processing, timing-driven layout, special clock distribution, and power distribution. The tool is currently being tested for designing the industry's most complex sea-of-gates gate arrays","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56680","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

Abstract

The authors present an automatic layout system for designing large sea-of-gates gate arrays. This tool combines a floorplanning tool with an automatic placement and routing tool. It is designed to handle 250 K-gate arrays with special functional blocks such as RAM and ROM. It provides features for current processing, timing-driven layout, special clock distribution, and power distribution. The tool is currently being tested for designing the industry's most complex sea-of-gates gate arrays
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一个分层地板规划,布局和路由工具的海门设计
提出了一种用于设计大型海闸门阵列的自动布局系统。该工具结合了地板规划工具与自动放置和路由工具。它设计用于处理具有特殊功能块(如RAM和ROM)的250 k门阵列。它提供了电流处理,时间驱动布局,特殊时钟分布和功率分布的功能。该工具目前正在测试设计业界最复杂的海门门阵列
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