Validating an ASIC standard cell library

Abstract

The accurate validation of the CHMOS III and CHMOS IV cell-based libraries is discussed. The validation methodology consists of library test chips which isolate each cell in a measurable and meaningful circuit. These chips use the customer design, layout, and simulation environment, incorporating all library cells. Manufacturing the test chip wafers across the worst-case process corners further guarantees that customer simulation bounds silicon performance. The characterization process encompasses process, temperature, and voltage extremes. For customer-specific operating conditions, K-factors for temperature and voltage are generated.<>