A 12Gb/s, 8.6µApp input sensitivity, monolithic-integrated fully differential optical receiver in CMOS 45nm SOI process

Abstract

A high-sensitivity, fully-differential optical receiver for high-density photonic interconnects is presented. To realize fully-differential operation, a 3-dB power splitter and SiGe photodetector are integrated with the receiver, all in a CMOS 45nm SOI process. The proposed receiver improves sensitivity by suppressing common-mode and supply noise through fully-differential (FD) operation, achieving 12Gb/s at BER <10−12 with input sensitivity of 8.6µAPP while consuming 4.3mW. To understand the effectiveness of the proposed solution, we compare it to a conventional single-ended (SE) receiver on the same test-chip. Measured sensitivity is >2× better than the closest state-of-the-art design, achieving same energy per bit at higher data-rate.