Implementation of a Round Robin Processing Element for Deep Learning Accelerator

Abstract

The deep learning acceleration hardwareperformance is greatly affected by Processing Elements (PEs). In order to apply deep learning accelerators to mobile devices, optimized PE must be designed as ASIC. To improve the performance of PE, we focused on methods of minimizing external memory access and parallelization. As a result, a deep learning accelerator architecture consisting of 512 PEs in parallel is proposed and the results of FPGA implementation is presented.