I-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, M. Ker
{"title":"Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product","authors":"I-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, M. Ker","doi":"10.1109/IPFA.2002.1025615","DOIUrl":null,"url":null,"abstract":"Latchup failure induced by ESD protection circuits occurred in a high-voltage IC product. Latchup occurred anomalously at only several output pins. All output pins have nearly identical layouts except the side output pin has a N-well resistor of RC gate-coupled PMOS beside. It was later found this N-well resistor is the main cause of inducing latchup.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2002.1025615","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17
Abstract
Latchup failure induced by ESD protection circuits occurred in a high-voltage IC product. Latchup occurred anomalously at only several output pins. All output pins have nearly identical layouts except the side output pin has a N-well resistor of RC gate-coupled PMOS beside. It was later found this N-well resistor is the main cause of inducing latchup.