New insight into stress induced voiding mechanism in Cu interconnects

Abstract

An effective method was used for the failure analysis of stress induced voids. Instead of conventional vertical inspection, the lower wide copper surface connected to the via was investigated after removing the passivation layer and upper copper layer. Many voids were observed at the grain boundary area, regardless of via location. According to the step by step inspection of that surface, many small voids were generated at the grain boundary area after dielectric barrier deposition, even before an HTS (high temperature storage) test, and some of the voids were grown after HTS, preferentially at the grain boundary corners. This result implies that unlucky landing of via over the grain boundary area would be the main cause of stress induced void under the via.