Wafer level packaging of RF MEMS devices using TSV interposer technology

Abstract

This paper presents the design, fabrication and characterization of MEMS wafer level packaging (WLP) with TSV based silicon interposer as cap wafer. High resistivity Si wafers have been used for TSV interposer fabrication mainly to minimize the intrinsic loss of RF MEMS device due to packaging. During development of this RF MEMS WLP, many key challenging processes have been developed such as, high aspect ratio TSV fabrication, double side RDL fabrication, thin wafer handling of TSV interposer and optimization of Au-Sn based TLP bonding. There are several fabrication steps involved in the actual process flow as, a) TSV fabrication and front side RDL patterning and passivation, b) Wafer thinning and backside RDL patterning and passivation c) UBM/ seal ring solder deposition and cavity formation, and d) TLP based wafer bonding of cap TSV interposer wafer with MEMS CPW wafer. Different CPW designs with three passivation schemes have been fabricated mainly to study the effect of passivation on insertion loss and ultimately quantify the packaging insertion loss. In pre-bonding testing, effect of passivation on insertion loss is thoroughly studied. After successful fabrication of the WLP, loss of RF device characteristics due to packaging has been studied. Before and after packaging, S-parameter measurements performed on coplanar waveguides (CPW). Amongst different passivation schemes, CPW structures with poly-silicon passivation have shown better performance.