A new multi-level timing simulation environment for timing verification

Abstract

The authors present a timing simulation environment that attempts to reduce the number of test patterns and features a novel multilevel timing simulator. In the proposed environment, the information contained in the logic description is used to recognize groups of test patterns that result in identical output transitions and therefore may be redundant. This information is also utilized to identify dormant subcircuits during the simulation. In addition, the authors describe a macromodeling methodology that provides multiple levels of modeling and further enhances the efficiency of the timing simulator