A 2.5-dB Insertion Loss, DC-60 GHz CMOS SPDT Switch in 45-nm SOI

Abstract

This paper presents a single-pole double-throw (SPDT), transmit/receive (T/R) switch operating from DC to 60 GHz. The SPDT switch is based on a series-shunt circuit with broadband input and output matching circuits and is implemented in a partially-depleted, 45-nm silicon-on-insulator (SOI) process. A buried oxide (BOX) layer is demonstrated to minimize substrate coupling. The switch exhibits a measured insertion loss of less than 1.7 dB at 45 GHz and less than 2.5 dB at 60 GHz with an isolation of greater than 25 dB at 45 GHz. To our knowledge, this is the lowest insertion loss demonstrated for an SPDT switch at 60 GHz in a CMOS process. With a control voltage of 1.2 V, the measured P1dB and IIP3 are 7.1 dBm and 18.2 dBm, respectively. The active chip area is 0.18×0.22 mm2.