{"title":"Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?","authors":"F. Fummi, C. Marconcini, G. Pravadelli","doi":"10.1109/ETSYM.2004.1347649","DOIUrl":null,"url":null,"abstract":"More and more functional verification is attracting EDA researchers and industrial companies interested in digital system validation. Coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck at fault model? The paper presents an accurate analysis of the correlation between the high-level bit coverage fault model and the gate-level stuck-at fault model.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ETSYM.2004.1347649","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
More and more functional verification is attracting EDA researchers and industrial companies interested in digital system validation. Coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck at fault model? The paper presents an accurate analysis of the correlation between the high-level bit coverage fault model and the gate-level stuck-at fault model.
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