Sub-quarter micron titanium salicide technology with in-situ silicidation using high-temperature sputtering

Abstract

A new titanium (Ti) salicide technology with in-situ silicidation using high-temperature sputtering has been developed. This process enhances TiSi/sub 2/ phase transition from C49 to C54 without agglomeration, which results in achieving silicidation in 0.2 /spl mu/m gates and 0.4 /spl mu/m diffusion layers. A sheet resistance less than 6/spl Omega///spl square/ can be obtained for both n/sup +/ and p/sup +/ silicide gates. CMOS transistors having 0.09 /spl mu/m effective channel length were successfully formed using the in-situ silicidation technique.