A current sense-amplifier for fast CMOS SRAMs

Abstract

A novel sense-amplifier circuit suitable for fast and large SRAMs in submicron CMOS technology has been proposed. The sense-amplifier is fast, yet very simple, comprising only four transistors. It features a current-sensing character, since it represents a virtual short-circuit to the bitlines, transferring the cell current directly to the output circuits. Sensing delay is rendered insensitive to bitline capacitance, thus easing one of the constraints in memory architecture design: that of restricted bitline length. Current consumption is decreased and yet speed is improved owing to an intrinsic precharge (or dynamic biasing) property. The virtual short-circuit character ensures equal bitline voltages, thus eliminating the need for bitline equalization during a read-access. This could also significantly affect architecture tradeoffs and chip access time