A novel packing algorithm for sparse crossbar FPGA architectures

Abstract

The cluster-based FPGA can significantly improve timing and routability. Packing is introduced in the CAD flow to pack logic elements into clusters. In order to reduce unnecessary connectivity within a cluster, sparse crossbar FPGA architectures are under investigation. This paper proposes a novel packing algorithm using direct graph searching method and connection gain function. Experimental results show that half populated crossbar FPGA architecture achieves 7% area improvement compared to fully populated counterpart with only 3% number of external nets overhead.