{"title":"Designing IEEE 1149.1 compatible boundary-scan logic into an ASIC using Texas Instrument's Scope architecture","authors":"J. Koeter","doi":"10.1109/ASIC.1990.186154","DOIUrl":null,"url":null,"abstract":"A design that was described and simulated behaviorally in Verilog, and synthesized and optimized using Synopsys, is discussed., IEEE 1149.1-compatible (Scope) logic was added to the optimized design and Mentor gate-level simulations were performed. The performance and area impact on the chip of the Scope logic is examined and synthesis is used to minimize it.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186154","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A design that was described and simulated behaviorally in Verilog, and synthesized and optimized using Synopsys, is discussed., IEEE 1149.1-compatible (Scope) logic was added to the optimized design and Mentor gate-level simulations were performed. The performance and area impact on the chip of the Scope logic is examined and synthesis is used to minimize it.<>
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