{"title":"A 130.3mW 16-core mobile GPU with power-aware approximation techniques","authors":"Yu-Jung Chen, Shan-Yi Chuang, Chung-Yao Hung, Chao-Hsien Hsu, Chia-Ming Chang, Shao-Yi Chien, Liang-Gee Chen","doi":"10.1109/ASSCC.2013.6691041","DOIUrl":null,"url":null,"abstract":"In this work, a 130mW 16-core mobile GPU is fabricated with TSMC 45nm technology. With three approximation techniques, this proposed architecture can trade-off between power consumption and visual quality to provide power-aware ability. Implementation results show that, with satisfactory visual quality, 53% of the power consumption can be reduced with the proposed Approximated Precision Shader architecture and Screen-space Approximated Lighting technique. Moreover, the Approximated Texturing technique reduces 24.57% L1 cache requests in our evaluation.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2013.6691041","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
In this work, a 130mW 16-core mobile GPU is fabricated with TSMC 45nm technology. With three approximation techniques, this proposed architecture can trade-off between power consumption and visual quality to provide power-aware ability. Implementation results show that, with satisfactory visual quality, 53% of the power consumption can be reduced with the proposed Approximated Precision Shader architecture and Screen-space Approximated Lighting technique. Moreover, the Approximated Texturing technique reduces 24.57% L1 cache requests in our evaluation.