Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS

2019 International SoC Design Conference (ISOCC) Pub Date : 2019-10-01 DOI:10.1109/ISOCC47750.2019.9027703

Yudai Ichii, R. Noguchi, Toshiyuki Inoue, A. Tsuchiya, K. Kishine

引用次数: 1

Abstract

This paper presents compensation circuit design for four-level pulse amplitude modulation (PAM4) transmitters with feed forward equalizing (FFE) in data transmission systems. The signal amplitude in PAM4 is small, particularly when the supply voltage is low. This leads to signal degradation. To maintain signal quality in PAM4 transmitters, we developed a design that performed within the appropriate combiner parameters. We conducted a post-layout simulation in an 180-nm CMOS process to confirm the advantage of the circuit. The rising and falling times were reduced by 7.4% and 2.4% compared with those of a conventional circuit.

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180nm CMOS PAM4变送器的适当补偿电路设计

提出了数据传输系统中具有前馈均衡的四电平脉冲调幅(PAM4)发射机的补偿电路设计。PAM4的信号幅值很小，特别是当电源电压较低时。这会导致信号退化。为了保持PAM4发射机的信号质量，我们开发了一种在适当的组合参数内执行的设计。我们在180nm CMOS工艺中进行了布局后仿真，以证实该电路的优势。与传统电路相比，上升和下降时间分别减少了7.4%和2.4%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2019 International SoC Design Conference (ISOCC)

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