A 4-bit 10GSample/sec flash ADC with merged interpolation and reference voltage

Abstract

A four-bit 10 GSample/sec flash analog-to-digital converter (ADC) with merged interpolation and reference voltage is presented. In this flash ADC, two clock-gated interpolation amplifiers are adopted and the number of resistor strings is reduced. An on-chip phase-locked loop is integrated to double sample the input signal and down sample the converted digital outputs, respectively. Furthermore, a digital-to-analog converter is embedded for the sake of measurements. This chip has been fabricated in 0.13 mum CMOS process and the ADCpsilas power consumption is 115 mW for a 1.2 V supply voltage. This ADC achieves the SNDR of 25 dB, INL of plusmn0.25 LSB, and DNL of plusmn0.5 LSB.