A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model

Zhongyuan Feng, Bo Wang, Zhaoyang Zhang, An Guo, Xin Si
{"title":"A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model","authors":"Zhongyuan Feng, Bo Wang, Zhaoyang Zhang, An Guo, Xin Si","doi":"10.1109/APCCAS55924.2022.10090256","DOIUrl":null,"url":null,"abstract":"Transformer model has achieved excellent results in many fields, owing of its huge data volume and high precision requirements, the traditional analog compute-in-memory circuit can no longer meet its needs. To solve this dilemma, this paper proposes a digital compute-in-memory circuit based on the improved Booth algorithm. The 6T SRAM array stores the multiplicand, and the multiplier is encoded by the booth encoder, and then, local computing cell (LCC) read the corresponding value from the array according to the encoding result. These values are finally sent to the dual-mode shift and add module (DMSA) to obtain the computation results. The proposed circuit achieved energy efficiency of 33.11TOPS/W@INT8 and 8.3 TOPS/W@INT16. And the proposed circuit achieved 1.92+ better energy efficiency compared with previous works.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS55924.2022.10090256","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

Transformer model has achieved excellent results in many fields, owing of its huge data volume and high precision requirements, the traditional analog compute-in-memory circuit can no longer meet its needs. To solve this dilemma, this paper proposes a digital compute-in-memory circuit based on the improved Booth algorithm. The 6T SRAM array stores the multiplicand, and the multiplier is encoded by the booth encoder, and then, local computing cell (LCC) read the corresponding value from the array according to the encoding result. These values are finally sent to the dual-mode shift and add module (DMSA) to obtain the computation results. The proposed circuit achieved energy efficiency of 33.11TOPS/W@INT8 and 8.3 TOPS/W@INT16. And the proposed circuit achieved 1.92+ better energy efficiency compared with previous works.
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基于展台的数字内存计算Marco处理变压器模型
变压器模型在许多领域取得了优异的成绩,由于其庞大的数据量和高精度要求,传统的模拟内存计算电路已不能满足其需求。为了解决这一难题,本文提出了一种基于改进Booth算法的数字内存计算电路。6T SRAM阵列存储乘数,乘数由展台编码器编码,然后本地计算单元(LCC)根据编码结果从阵列读取相应的值。最后将这些值发送给双模移位和加法模块(DMSA)以获得计算结果。该电路的能量效率分别为33.11TOPS/W@INT8和8.3 TOPS/W@INT16。与以往的工作相比,该电路的能效提高了1.92+。
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