A 30V 2A Real-Time Programmable Solid-State Circuit Breaker with Improved Detection-Speed and Enhanced Power-Efficiency

Yong Qu, Wei Shu, Y. Kang, J. Chang
{"title":"A 30V 2A Real-Time Programmable Solid-State Circuit Breaker with Improved Detection-Speed and Enhanced Power-Efficiency","authors":"Yong Qu, Wei Shu, Y. Kang, J. Chang","doi":"10.1109/ESSCIRC.2019.8902522","DOIUrl":null,"url":null,"abstract":"State-of-the-art circuit breakers embodying a predetermined fixed current limit exhibit difficulty in differentiating large inrush current during startups and gentle overcurrent during on-state with load, and thus often fail to provide prompt protection. This paper presents a monolithically integrated solid-state circuit breaker that features a variable current limit by means of employing our proposed real-time programmable current limit controller, low quiescent current by our proposed Darlington-LDMOS-based high-voltage regulator, and fast detection speed by our improved on-chip LDPMOS current sensor. The prototype circuit breaker, realized in a 130nm BCDLite process, features a programmable current limit range of 0.2-2A, maximum input voltage of 30V, quiescent current of 30µA, and fault-current response time of 0.2µs. When benchmarked against the state-of-the-art solid-state circuit breakers, our design simultaneously features the widest current limit range, highest input voltage handling capability, ~13× lower quiescent current, and ~5× shorter response time.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902522","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

State-of-the-art circuit breakers embodying a predetermined fixed current limit exhibit difficulty in differentiating large inrush current during startups and gentle overcurrent during on-state with load, and thus often fail to provide prompt protection. This paper presents a monolithically integrated solid-state circuit breaker that features a variable current limit by means of employing our proposed real-time programmable current limit controller, low quiescent current by our proposed Darlington-LDMOS-based high-voltage regulator, and fast detection speed by our improved on-chip LDPMOS current sensor. The prototype circuit breaker, realized in a 130nm BCDLite process, features a programmable current limit range of 0.2-2A, maximum input voltage of 30V, quiescent current of 30µA, and fault-current response time of 0.2µs. When benchmarked against the state-of-the-art solid-state circuit breakers, our design simultaneously features the widest current limit range, highest input voltage handling capability, ~13× lower quiescent current, and ~5× shorter response time.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
一种30V 2A实时可编程固态断路器,具有改进的检测速度和增强的功率效率
最先进的断路器包含预定的固定电流限制,在区分启动时的大涌流和带负载的导通状态时的轻微过流方面表现出困难,因此经常不能提供及时的保护。本文提出了一种单片集成的固态断路器,该断路器采用我们提出的实时可编程限流控制器,具有可变限流,我们提出的基于darlington - ldmos的高压稳压器具有低静态电流,以及我们改进的片上LDPMOS电流传感器具有快速检测速度。该原型断路器采用130nm BCDLite工艺实现,可编程限流范围为0.2- 2a,最大输入电压为30V,静态电流为30µa,故障电流响应时间为0.2µs。当与最先进的固态断路器进行基准测试时,我们的设计同时具有最宽的电流限制范围,最高的输入电压处理能力,~ 13x低静态电流和~ 5x短响应时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO An Integrated Programmable High-Voltage Bipolar Pulser With Embedded Transmit/Receive Switch for Miniature Ultrasound Probes Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR An 18 dBm 155-180 GHz SiGe Power Amplifier Using a 4-Way T-Junction Combining Network A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1