Naftali Weiss, S. Shopov, P. Schvan, P. Chevalier, A. Cathelin, S. Voinigescu
{"title":"DC-62 GHz 4-phase 25% duty cycle quadrature clock generator","authors":"Naftali Weiss, S. Shopov, P. Schvan, P. Chevalier, A. Cathelin, S. Voinigescu","doi":"10.1109/CSICS.2017.8240468","DOIUrl":null,"url":null,"abstract":"A process-, temperature-and supply-insensitive DC-to-62GHz 4-phase quadrature generator for clock signals with 25% duty cycle was manufactured in a production 55-nm SiGe BiCMOS technology. The purely digital circuit is based on a 2.5 V bipolar-CML static divider, AND gates and inverter stages, and operates with input signals from DC to 124 GHz while consuming 178 mW. Measurements were conducted with 63-GHz and 100-GHz bandwidth real-time oscilloscopes. The measured self-oscillation frequency of the static divider in the generator was 98.8 GHz, compared to 93 GHz in simulation. The measured output signals remained in quadrature up to 62 GHz. The measured duty cycle is 25–26% up to 30 GHz and increases up to 33% at 50 GHz, beyond which measurements are impacted by the limited bandwidth of the oscilloscope. The simulated duty cycle was lower than 28% up to 62 GHz.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"185 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2017.8240468","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
A process-, temperature-and supply-insensitive DC-to-62GHz 4-phase quadrature generator for clock signals with 25% duty cycle was manufactured in a production 55-nm SiGe BiCMOS technology. The purely digital circuit is based on a 2.5 V bipolar-CML static divider, AND gates and inverter stages, and operates with input signals from DC to 124 GHz while consuming 178 mW. Measurements were conducted with 63-GHz and 100-GHz bandwidth real-time oscilloscopes. The measured self-oscillation frequency of the static divider in the generator was 98.8 GHz, compared to 93 GHz in simulation. The measured output signals remained in quadrature up to 62 GHz. The measured duty cycle is 25–26% up to 30 GHz and increases up to 33% at 50 GHz, beyond which measurements are impacted by the limited bandwidth of the oscilloscope. The simulated duty cycle was lower than 28% up to 62 GHz.