K. Watabe, H. Akiyama, T. Terashima, S. Nobuto, M. Yamawaki, T. Hirao
{"title":"A 0.8 /spl mu/m high voltage IC using newly designed 600 V lateral IGBT on thick buried-oxide SOI","authors":"K. Watabe, H. Akiyama, T. Terashima, S. Nobuto, M. Yamawaki, T. Hirao","doi":"10.1109/ISPSD.1996.509469","DOIUrl":null,"url":null,"abstract":"We have demonstrated that the developed process has a breakdown voltage of higher than 600 V with use of thick buried-oxide and thin SOI. From both experiments and simulations, the cylindrical structure in the LIGBTs shows the best performance; it improves the latch-up tolerance without the increase of on-state voltage. Moreover, the process we have developed is completely compatible with an existing 5 V, 0.8 /spl mu/m CMOS process.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1996.509469","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
We have demonstrated that the developed process has a breakdown voltage of higher than 600 V with use of thick buried-oxide and thin SOI. From both experiments and simulations, the cylindrical structure in the LIGBTs shows the best performance; it improves the latch-up tolerance without the increase of on-state voltage. Moreover, the process we have developed is completely compatible with an existing 5 V, 0.8 /spl mu/m CMOS process.