Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509513
H. Takahashi, H. Haruguchi, H. Hagino, T. Yamada
A new device concept, called the Carrier Stored Trench-Gate Bipolar Transistor (CSTBT) is reported for the first time. The CSTBT forms the n layer under p base between trenches, the n layer stores carriers; as aesult, the carrier distribution of the CSTBT becomes that of the diode. We examined the performance of the CSTBT by simulation and experiment in the case of the blocking voltage of 1700 V, compared to the simple trench IGBT (TIGBT) and the PiN diode. This confirmed the CSTBT is superior to the TIGBT, and the on-state voltage of the CSTBT is almost same as the Vf of the PiN diode. By the fabricated CSTBT, on-state voltage is 1.9 V at 50 A/cm/sup 2/, turn-off time of resistive load switching is about 300 nsec. We realized turn-off current capability of the CSTBT above 250 A/cm/sup 2/.
{"title":"Carrier stored trench-gate bipolar transistor (CSTBT)-a novel power device for high voltage application","authors":"H. Takahashi, H. Haruguchi, H. Hagino, T. Yamada","doi":"10.1109/ISPSD.1996.509513","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509513","url":null,"abstract":"A new device concept, called the Carrier Stored Trench-Gate Bipolar Transistor (CSTBT) is reported for the first time. The CSTBT forms the n layer under p base between trenches, the n layer stores carriers; as aesult, the carrier distribution of the CSTBT becomes that of the diode. We examined the performance of the CSTBT by simulation and experiment in the case of the blocking voltage of 1700 V, compared to the simple trench IGBT (TIGBT) and the PiN diode. This confirmed the CSTBT is superior to the TIGBT, and the on-state voltage of the CSTBT is almost same as the Vf of the PiN diode. By the fabricated CSTBT, on-state voltage is 1.9 V at 50 A/cm/sup 2/, turn-off time of resistive load switching is about 300 nsec. We realized turn-off current capability of the CSTBT above 250 A/cm/sup 2/.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125471226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509477
T. Fowler, R. Kollman, T. Efland, D. Skelton
Pulse width modulation (PWM) techniques have been limited to 1 to 2 MHz by the switching speeds of currently available power switches. This limitation has been overcome by high speed (<2 nanosecond) switching with improved 1 /spl mu/m PMOS transistors. These devices have been incorporated in a 5 MHz, PWM buck power stage that has demonstrated good efficiency (>85%) and very high power density (500 W/in/sup 3/ versus state-of-the-art 100 W/in/sup 3/).
{"title":"Multi-megahertz pulse width modulation converters with improved 1 /spl mu/m p-channel metal oxide semiconductor transistors","authors":"T. Fowler, R. Kollman, T. Efland, D. Skelton","doi":"10.1109/ISPSD.1996.509477","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509477","url":null,"abstract":"Pulse width modulation (PWM) techniques have been limited to 1 to 2 MHz by the switching speeds of currently available power switches. This limitation has been overcome by high speed (<2 nanosecond) switching with improved 1 /spl mu/m PMOS transistors. These devices have been incorporated in a 5 MHz, PWM buck power stage that has demonstrated good efficiency (>85%) and very high power density (500 W/in/sup 3/ versus state-of-the-art 100 W/in/sup 3/).","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123626187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509446
T. Abe, M. Katayama
A survey is presented of bonded SOI (BSOI) applications utilizing silicon layers of thickness from 0.1 /spl mu/m to 60 /spl mu/m. Description of the fabrication process and properties of standard BSOI is given. For high voltage applications,the various bonded structures and material issues are described and compared to SIMOX (separation by implanted oxygen). New thinning technologies for ultra-thin SOI (<0.1 /spl mu/m) including recently developed method for separation at an implanted plane are briefly discussed.
{"title":"Bonded SOI technologies for high voltage applications","authors":"T. Abe, M. Katayama","doi":"10.1109/ISPSD.1996.509446","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509446","url":null,"abstract":"A survey is presented of bonded SOI (BSOI) applications utilizing silicon layers of thickness from 0.1 /spl mu/m to 60 /spl mu/m. Description of the fabrication process and properties of standard BSOI is given. For high voltage applications,the various bonded structures and material issues are described and compared to SIMOX (separation by implanted oxygen). New thinning technologies for ultra-thin SOI (<0.1 /spl mu/m) including recently developed method for separation at an implanted plane are briefly discussed.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"77 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113978111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509484
J. Dilhac, D. Zerrouk, C. Ganibal, P. Rossel, M. Bafleur
We present new experimental results about a method for creating thick silicon films on localized buried oxide layers, by superficial melting and solidification using a bank of tungsten halogen lamps. The purpose of this technique is to obtain cost-effective "partially SOI" substrates for high voltage smart power applications. Chemical defect revelation has been carried out in the SOI and seeded regions. N-channel MOSFETs have also been fabricated. It appears that crystallographic and electrical quality is sufficient for device processing.
{"title":"Fabrication of SOI structures by uniform zone melting recrystallization for high voltage ICs","authors":"J. Dilhac, D. Zerrouk, C. Ganibal, P. Rossel, M. Bafleur","doi":"10.1109/ISPSD.1996.509484","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509484","url":null,"abstract":"We present new experimental results about a method for creating thick silicon films on localized buried oxide layers, by superficial melting and solidification using a bank of tungsten halogen lamps. The purpose of this technique is to obtain cost-effective \"partially SOI\" substrates for high voltage smart power applications. Chemical defect revelation has been carried out in the SOI and seeded regions. N-channel MOSFETs have also been fabricated. It appears that crystallographic and electrical quality is sufficient for device processing.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125750639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509481
J. Sanchez, P. Leturcq, P. Austin, R. Berriane, M. Breil, C. Anceau, C. Ayela
This paper describes the design and fabrication of new two-terminal semiconductor devices, based on the concept of "functional integration", acting as current limiter for high voltage applications (400 V to 1,000 V). In the first section, the optimization of structures and fabrication processes are considered using 2D simulation tools SUPREM IV and PISCES. In the second section, the first experimental results of these devices are presented.
{"title":"Design and fabrication of new high voltage current limiting devices for serial protection applications","authors":"J. Sanchez, P. Leturcq, P. Austin, R. Berriane, M. Breil, C. Anceau, C. Ayela","doi":"10.1109/ISPSD.1996.509481","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509481","url":null,"abstract":"This paper describes the design and fabrication of new two-terminal semiconductor devices, based on the concept of \"functional integration\", acting as current limiter for high voltage applications (400 V to 1,000 V). In the first section, the optimization of structures and fabrication processes are considered using 2D simulation tools SUPREM IV and PISCES. In the second section, the first experimental results of these devices are presented.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134603154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509445
S. Anderson
This paper discusses three applications of GaAs rectification. The first application is a 600 V GaAs rectifier for power factor correction, the second is the low voltage application of GaAs in synchronous rectification and the third application is a medium voltage GaAs rectifier in output rectification. These applications of GaAs rectification demonstrate the potential performance improvement of this technology. Applications that can justify the cost of GaAs generally benefit in terms of switching performance at elevated temperature or ultra-low Rdson as shown by the examples in this paper.
本文讨论了砷化镓整流的三种应用。第一个应用是用于功率因数校正的600 V GaAs整流器，第二个应用是用于同步整流的GaAs低压应用，第三个应用是用于输出整流的中压GaAs整流器。这些GaAs整流的应用证明了该技术的潜在性能改进。可以证明砷化镓成本的应用通常在高温或超低Rdson下的开关性能方面受益，如本文中的示例所示。
{"title":"GaAs rectification-an enabling technology for high frequency operation of power MOS-gated transistors","authors":"S. Anderson","doi":"10.1109/ISPSD.1996.509445","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509445","url":null,"abstract":"This paper discusses three applications of GaAs rectification. The first application is a 600 V GaAs rectifier for power factor correction, the second is the low voltage application of GaAs in synchronous rectification and the third application is a medium voltage GaAs rectifier in output rectification. These applications of GaAs rectification demonstrate the potential performance improvement of this technology. Applications that can justify the cost of GaAs generally benefit in terms of switching performance at elevated temperature or ultra-low Rdson as shown by the examples in this paper.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130978426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509475
F. Vogt, H. Vogt, J. Brucker, C. Zimmermann, F. Richter
This paper describes first results of a monolithically integrated smart power device which uses a vertical Trench-DMOS as a power switch and a signal and control circuit fabricated in a SOI-CMOS technology (SOI: silicon on insulator). The vertical dielectric isolation between the Trench-DMOS and the control circuit is formed by the SIMOX-Process (SIMOX: separation by implanted oxygen) and the lateral isolation is realized by the LOGOS technology. The self-protection of the entire device is achieved by measuring the temperature and the load current of the power transistor. The protection is provided by analog and digital CMOS circuits with a supply voltage of 15 V. This device can be used, for example, as an "intelligent" switch in a dimmer circuit for automotive application.
{"title":"An intelligent vertical trench DMOS on SIMOX-substrate","authors":"F. Vogt, H. Vogt, J. Brucker, C. Zimmermann, F. Richter","doi":"10.1109/ISPSD.1996.509475","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509475","url":null,"abstract":"This paper describes first results of a monolithically integrated smart power device which uses a vertical Trench-DMOS as a power switch and a signal and control circuit fabricated in a SOI-CMOS technology (SOI: silicon on insulator). The vertical dielectric isolation between the Trench-DMOS and the control circuit is formed by the SIMOX-Process (SIMOX: separation by implanted oxygen) and the lateral isolation is realized by the LOGOS technology. The self-protection of the entire device is achieved by measuring the temperature and the load current of the power transistor. The protection is provided by analog and digital CMOS circuits with a supply voltage of 15 V. This device can be used, for example, as an \"intelligent\" switch in a dimmer circuit for automotive application.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"86 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133391652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509487
R. Saitoh, M. Yoshino, M. Otsuki, K. Sukurai
By a simulation study and advanced process technologies, the edge termination structure has been modified for a high power electronic industrial applications and traction. In the rail traction application, the power devices may be subjected to both high voltage and high current at a relative low ambient temperature. In this field, a specified maximum blocking voltage is strongly requested even at the low ambient temperature of -40/spl deg/C. The temperature dependence of the blocking voltage is strongly dependent on the edge termination structure. We developed a high voltage IGBT having a lower temperature dependence of the blocking voltage, which has an edge termination with a semi-resistive film over field limiting rings with the offset field plates. This technology will spread the application field of IGBT toward higher voltages and more demanding operating conditions.
{"title":"A study on edge termination technique at low temperature for high voltage IGBT","authors":"R. Saitoh, M. Yoshino, M. Otsuki, K. Sukurai","doi":"10.1109/ISPSD.1996.509487","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509487","url":null,"abstract":"By a simulation study and advanced process technologies, the edge termination structure has been modified for a high power electronic industrial applications and traction. In the rail traction application, the power devices may be subjected to both high voltage and high current at a relative low ambient temperature. In this field, a specified maximum blocking voltage is strongly requested even at the low ambient temperature of -40/spl deg/C. The temperature dependence of the blocking voltage is strongly dependent on the edge termination structure. We developed a high voltage IGBT having a lower temperature dependence of the blocking voltage, which has an edge termination with a semi-resistive film over field limiting rings with the offset field plates. This technology will spread the application field of IGBT toward higher voltages and more demanding operating conditions.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117096027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509444
B. Murari, D. Rossi
This paper reviews the latest trends in the use of integrated circuits in motor control and the consequences of recent integrated circuit technology developments on the designs of motor control subsystems. Three segments are analyzed in detail: portable equipment, domestic appliances and automotive electronics. In addition, new device packaging concepts for motor driving ICs are described.
{"title":"Power ICs in motor control","authors":"B. Murari, D. Rossi","doi":"10.1109/ISPSD.1996.509444","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509444","url":null,"abstract":"This paper reviews the latest trends in the use of integrated circuits in motor control and the consequences of recent integrated circuit technology developments on the designs of motor control subsystems. Three segments are analyzed in detail: portable equipment, domestic appliances and automotive electronics. In addition, new device packaging concepts for motor driving ICs are described.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123719168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-20DOI: 10.1109/ISPSD.1996.509458
H. Funaki, N. Yasuhara, A. Nakagawa
A high voltage lateral MOS thyristor cascode switch on SOI was proposed. It consists of a high voltage MOS thyristor, a low voltage MOSFET and a pn diode. Excellent on-state and switching characteristics were numerically and experimentally obtained. The safe operating area (SOA) of SOI-Resurf devices were discussed.
{"title":"High voltage lateral MOS thyristor cascode switch on SOI-safe operating area of SOI-Resurf devices","authors":"H. Funaki, N. Yasuhara, A. Nakagawa","doi":"10.1109/ISPSD.1996.509458","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509458","url":null,"abstract":"A high voltage lateral MOS thyristor cascode switch on SOI was proposed. It consists of a high voltage MOS thyristor, a low voltage MOSFET and a pn diode. Excellent on-state and switching characteristics were numerically and experimentally obtained. The safe operating area (SOA) of SOI-Resurf devices were discussed.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126883055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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