An eyperimental 1Mb cache DRAM with ECC

Abstract

In the recent progress of the micro procesaor unit (MPU), requirements for fast accom a p e d memories have become strong. And a cost-effective cache subsystem is desired for the low-end work station and the personal computer. On the other hand, as for DRAMs, problems of the reliability such as a-particle induced soft e r " will be more serious according to the increase of density. To overcome these problems, the DRAMs with on-chip ECC (Error Checking and Correcting) circuit were reportcd.l".12' But using ECC circnit, the access a p e d is delayed to d e t n t and Correct errors. This paper presents the newly proposed CACHE DRAM with the ECC circuit. This ECC circuit improves the reliability of the DRAM data. And on-chip cache =heme can provide a high-speed data mapping and relieve an access time loss for error correction and w reduces the average access time.