Challenges of modeling the Split-Gate SuperFlash® Memory Cell with 1.1V Select Transistor

Abstract

In this paper we discuss key challenges related to application of an accurate 2T cell model for robust array design in 40nm CMOS technology and how an improved model behavior is used to overcome the challenges. The main challenge is the extraction of model parameters for word line (WL) and floating gate (FG) transistors in the absence of access to the FG. A global optimization scheme with an improved data collection strategy enabled the extraction of a comprehensive set of model parameters. This makes the separation of mobility parameters of WL and FG transistors possible.