An Energy-Efficient Readout Circuit Based on Incremental Delta-Sigma ADC with Decimation Filter for CMOS Image Sensors

Abstract

This paper presents an energy-efficient readout circuit based on incremental delta-sigma ADC (IADC) with a decimation filter for CMOS image sensors (CIS). A single-end 3rd-order 1-bit inverter-based delta-sigma ADC is embedded to achieve high resolution conversion efficiently. In addition, the correlated level shifting (CLS) technique was adopted, which enhances the DC gain of the integrator from 42.7 dB to 62.4 dB and extends the output swing from 85% to 100% of the full scale. A compact decimation filter with digital correlation double sampling (CDS) was used, which consists of only a counter and two digital integrators. The prototype chip is designed in a 55 nm CMOS process with a 1.2V supply voltage. Transient noise post-simulation results reveal the decimation filter consumes $\boldsymbol{33.0}\ \mu\mathbf{W}$ and the IADC consumes $\boldsymbol{30.2}\ \mu \mathbf{W}$ while achieving 82.8 dB SNR in 25 $\boldsymbol{\mu}\mathbf{s}$ conversion time, resulting in a Schreier FoM of 171.0 dB.