A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST

Abstract

An embedded DRAM macro fabricated in 65 nm CMOS achieves 1.0 GHz multi-banked operation at 1.0 V yielding 584 Gbits/sec. The array utilizes a 0.1 1 mum2 cell with 20 fF deep trench capacitor and 2.2 nm gate oxide transfer gate. Concurrent refresh allows for high availability via a second bank address. At-speed test and repair is accomplished with a new hierarchical BIST architecture. Measured random cycle time exceeds 333 MHz at 1.0 V with functional operation from 750 mV to 1.5 V and densities up to 36.5 Mbits.