Suppression Of Bit-line-induced Disturbance In SOI DRAM/SRAM Cells By Bipolar Embedded Source Structure (BESS)

Abstract

The disturbance of stored charges in SO1 memory cells, which is caused by floating body effects, is fully suppressed by using an access transistor with a bipolar embedded source structure just beneath the n'junction. This structure is free from the subthreshold leakage current and degradation caused by high source resistance. Introduction The use of SO1 in future-generation DRAM technology promises to facilitate the wide spread of SO1 CMOS as the main technology for ULSI systems. The greatestbarrier that stands in the way of this is the notorious floating body effects which cause bit-line-induced disturbances in memory cells [l]. In Sol, minority carriers generated in the body forward bias the body-bit-line diode when the bit-line potential falls to a low level. This forward junction injects minority caniers across the channel into the storage node, upsetting the stored charge even if the word line is deactivated This type of disturbance seriously shortens the dynamic retention characteristicsor, in other words degrade the refresh time properties. This paper presents a possible solution that fully suppresses the floating body effects and bit-line-induced disturbances in SOICMOSFETs without sacrificing their excellent performance. Device Outline A schematic cross-section of a bipolar embedded source structure (BESS) device [2] is shown in Fig. 1. In an nchannel access transistor, p-type recombination centers are embedded in the nsourcddrain regions adpen t to the SOUburied oxide interface. A generated hole in the p-type body can easily diffuse to a source recombination center through the nsource bypass which has a low built-in potential barrier. Thus, hole recombination in the source prevents the floating body problems. /cmZ) with a projection range to the SOI/buried oxide interface followed by recrystallization annealing creates the recombination centers, leading to the formation of a small grain poly-Si region. This structure is independent of the source /drain profile near the gate edges, and there is no degradation of device properties. The bit-line induced disturbance in the SO1 DRAM cells can be evaluated with the simple test circuit shown in Fig. 2. In the test circuit, the storagecapacitor (Cpad=0.75 pF)) was made by connecting two bonding pads of the accessand sense-transistors with a conductive paste. The on-wafer measurements were carried out with an external load resistor connected to the sense transistor. High-dose Si implanted amorphization Simulated Results The forward hole current properties at the source diode are directly related to the floating-body-immune properties. A numerical simulation of a fonvard-biased (0.5 V) potential contour in a BESS diode is shown in Fig. 3. The simulated profile shows that the potential falls near the buried oxide interface due to the dielectric discontinuity. The hole current density vector simulated in Fig. 4(a) also shows that a higher current flow can be observedjust above the buriedoxideinterface at a forward bias of 0.5 V. At a hgher forward bias (0.7 V), this tenckncy is not as well &fined and the hole current flows through a wide area of the cross-section. The forward hole current properties of BESS diode depend on of the width Wb, concentration Nb, andcross-section of the nregion. Also, the concentration of the body Na and the recombination centers N, also affect the properties. The simulated forward hole current dependence on Nais shown in Fig. 5. An increasein the hole current flow from the body to the source of more than five decades is predicted in comparison with that of the conventional n+ source. Experimental Results Poly-Si gate n-MOSFETs with the BESS were fabricated in a 200 + 10-nm-thick SO1 layer with a 500-nm-thick buried oxide. The highest annealing temperature after Si implantation was 900 "C. Sourddrain Ti-silicidation was carried out for some samples. Typical current-voltage characteristics of both conventional SO1 andBESS SO1 devices without silicidation areshown in Fig. 6. Neither kinks nor an increase in source resistance can be seen in the results from the BESS devices. The breakdown voltage of the BESS &vice was 7 V, which is equal to that of a bulk device, and two times as high as that of a conventional SO1 device. In the subthreshold swing of the BESS device shown in Fig. 7, there is no leakage current or abnormal self-latch phenomena. The drain-induced barrier-lowering effect is significantly improved by the BESS technique as is clearly shown in Fig. 8. The experimentally observed electrical properties shown above prove that the BESS technique fully suppresses the floating body effects without causing any serious problems. The bit-line-induced-disturbance is shown in Figs. 9 and 10. Parameters are the bit-line high-level pulse width t,, and the height of the low-level bit-line pulse V,L. It is clear that the dynamic retention time (defined as the time required for the signal to decrease to 60 %) is significantly improved by the BESS technique without showing any effects of bit-line-induced disturbance. Conclusion The BESS technique significantly improves SO1 device reliability by suppressing the floating body effects and is free of bit-line-induced disturbance, which makes it extremely useful for future generation SOL DRAMISRAM. We expect this technique to help lead the way to the wide use of SO1 in ULSI systems. References [l] F. Morishita et al.; Symp. VLSITech. p.141 (1995) [2] M. Horiuchi and M. Tamura; Tech. Dig. IEDM, 5.5, (1996) 157 4-93081 3-75-1 197 1997 Symposium on VLSl Technology Digest of Technical Papers