{"title":"Special session 11B: Hot topic on-chip clocking — Industrial trends","authors":"A. Chandra","doi":"10.1109/VTS.2013.6548942","DOIUrl":null,"url":null,"abstract":"A typical design today is implemented with DFT where the capture clocks are supplied on chip. The on-chip controller (OCC) plays a critical role in the application and the quality of the tests. Almost every design house has developed an innovative way of delivering either the structural tests or in house mix of structural-functional tests through the use of OCC and the design-for-test (DFT) implemented on the chip. Complexities in the implementation come due to the various test strategies employed with: • Process variation leading to issues like dealing with non-unique critical paths on every chip • Test data compression becoming primary DFT solution for manufacturing test • Low cost testers unable to keep up with the requirements of clocking schemes In this session, we want to explore the current offerings of the EDA tools to implement OCC based solutions and how the industry is going beyond those standard solutions to use innovative OCC based tests to provide a quality at-speed manufacturing test solution.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 31st VLSI Test Symposium (VTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTS.2013.6548942","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A typical design today is implemented with DFT where the capture clocks are supplied on chip. The on-chip controller (OCC) plays a critical role in the application and the quality of the tests. Almost every design house has developed an innovative way of delivering either the structural tests or in house mix of structural-functional tests through the use of OCC and the design-for-test (DFT) implemented on the chip. Complexities in the implementation come due to the various test strategies employed with: • Process variation leading to issues like dealing with non-unique critical paths on every chip • Test data compression becoming primary DFT solution for manufacturing test • Low cost testers unable to keep up with the requirements of clocking schemes In this session, we want to explore the current offerings of the EDA tools to implement OCC based solutions and how the industry is going beyond those standard solutions to use innovative OCC based tests to provide a quality at-speed manufacturing test solution.