Potential of low temperature CMOS with normal and superconductive interconnect

Abstract

The potential of high-T/sub c/ superconductive interconnects in CMOS-based digital systems is examined theoretically using system simulation, a new design tool for electronic packages and systems. A 1.5- mu m-technology CMOS processor, with 500000 circuits partitioned into 25 chips packaged as a single multichip module, is examined. The best implementation with superconductive interconnects at 77 K has a cycle time of 9.6 ns, which is about six times faster than the baseline design with normal metal (Al, Cu) interconnects at 300 K.<>