A Wideband Low-Noise Inductor less CMOS Active Mixer With Improved Linearity

Hesam Abbasi, M. Yavari
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引用次数: 1

Abstract

This paper presents a CMOS active inductorless downconversion mixer for zero-IF receivers. The structure implements the 1M2 injection and derivative superposition techniques to improve the linearity. Nonlinear currents are generated by auxiliary transistors and they are injected to the nonlinear currents of the input transistors into increase the second-order input intercept point (IIP2) and third-order input intercept point (IIP3) values of the mixer. Common-Gate structure is used in the RF input stage. To reduce the noise contribution of the input transistors, a noise cancellation technique is employed. The proposed mixer is designed in 65 nm CMOS technology and simulated using Spectre-RF in Cadence. The simulation results show 8.34 dB, 6.81 dB, and 4.15 dB on average improvement for IIP2, IIP3, and NF, respectively, in the 0.8-5 GHz input frequency range. The proposed mixer consumes 13.95 mW power which is 64.1% more than the conventional CMOS active mixer.
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改进线性度的宽带低噪声无电感CMOS有源混频器
提出了一种用于零中频接收机的CMOS有源无电感下变频混频器。该结构实现了1M2注入和导数叠加技术,以提高线性度。非线性电流由辅助晶体管产生,注入到输入晶体管的非线性电流中,以增加混频器的二阶输入截点(IIP2)和三阶输入截点(IIP3)值。射频输入级采用共门结构。为了降低输入晶体管的噪声贡献,采用了噪声消除技术。所提出的混频器采用65nm CMOS技术设计,并在Cadence中使用Spectre-RF进行仿真。仿真结果表明,在0.8 ~ 5 GHz输入频率范围内,IIP2、IIP3和NF分别平均提高了8.34 dB、6.81 dB和4.15 dB。该混合器功耗为13.95 mW,比传统CMOS有源混合器功耗高64.1%。
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