{"title":"Implementation of a cost efficient SSL based on an Angular beamformer SRP-PHAT","authors":"H. Zarghi, M. Sharifkhani, I. Gholampour","doi":"10.1109/ICECS.2011.6122211","DOIUrl":null,"url":null,"abstract":"Among Sound Source Localization (SSL) methods, beamformed microphone arrays using Steering Response Power(SRP) has received significant attention. Yet, its application is stumbled by its computational complexity which cannot meet low-power/low-cost applications requirements. In this paper, Angular beamforming is presented. By applying this beamforming approach to the conventional SRP-PHAT one can find that the complexity of SRP-PHAT will decreased by two orders of magnitudes with a mere three fold reduction in resolution. The proposed method is implemented both on FPGA and 0.18um CMOS technology for a practical case.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2011.6122211","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Among Sound Source Localization (SSL) methods, beamformed microphone arrays using Steering Response Power(SRP) has received significant attention. Yet, its application is stumbled by its computational complexity which cannot meet low-power/low-cost applications requirements. In this paper, Angular beamforming is presented. By applying this beamforming approach to the conventional SRP-PHAT one can find that the complexity of SRP-PHAT will decreased by two orders of magnitudes with a mere three fold reduction in resolution. The proposed method is implemented both on FPGA and 0.18um CMOS technology for a practical case.